A practical methodology for early buffer and wire resource allocation

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 189-194

  Alpert, Charles J ^a   Hu, Jiang ^a   Sapatnekar, Sachin S ^a,b   Villarrubia, Paul G ^a  

^a IBM   (United States)

^b University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER STORAGE; HEURISTIC METHODS; RESOURCE ALLOCATION;

BUFFER BLOCK PLANNING;

VLSI CIRCUITS;

EID: 0034841272     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2001.156133     Document Type: Article

References (8)

1. Prim-dijkstra tradeoffs for improved performance-driven routing tree design
2. An interconnect-centric design flow for Nanometer technologies
3. Buffer block planning for interconnect-driven floorplanning
4. Provably good global buffering using an available buffer block plan
5. Provably good global buffering by multiterminal multicommodity flow approximation
6. Routability-driver repeater block planning for interconnect-centric floorplanning
7. Planning buffer locations by network flows
8. Buffer placement in distributed RC-tree networks for minimal elmore delay