Buffered Steiner trees for difficult instances

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 1, 2002, Pages 3-14

  Alpert, Charles J ^a,b   Gandham, Gopal ^b   Hrkic, Milos ^c   Hu, Jiang ^b   Kahng, Andrew B ^d   Lillis, John ^c   Liu, Bao ^c   Quay, Stephen T ^b   Sapatnekar, Sachin S ^e   Sullivan, A J ^b  

^a IEEE   (United States)

^b IBM   (United States)

^c University of Illinois at Chicago   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e University of Minnesota   (United States)

Author keywords

Buffer insertion; Global routing; Interconnect synthesis; Steiner tree

Indexed keywords

BUFFERED STEINER TREES;

ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS; OPTIMIZATION; TREES (MATHEMATICS);

INTEGRATED CIRCUIT LAYOUT;

EID: 0036180537     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.974132     Document Type: Article

References (23)

1. Wire segmenting for improved buffer insertion
2. Buffer insertion for noise and delay optimization
3. Buffer insertion with accurate gate and interconnect delay computation
4. Steiner tree optimization for buffers, blockages and bays
5. Prim-Dijkstra tradeoffs for improved performance-driven routing tree design
6. Near-optimal critical sink routing tree constructions
7. Closed form solution to simultaneous buffer insertion/sizing and wire sizing
8. Challenges and opportunities for design innovations in nanometer technologies
9. Performance optimization of VLSI interconnect layout
10. Performance-driven interconnect design based on distributed RC delay mode
11. Routing tree construction under fixed buffer locations
12. Optimum buffer circuits for driving long uniform lines
13. The transient response of damped linear network with particular regard to wideband amplifiers
14. Clustering to minimize the maximum intercluster distance
15. A fast algorithm for context-aware buffer insertion
16. Maze routing with buffer insertion and wire-sizing
17. New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing
18. Optimal wire sizing and buffer insertion for low power and a generalized delay model
19. Simultaneous routing and buffer insertion for high performance interconnect
20. Buffered Steiner tree construction with wire sizing for interconnect layout optimization
21. Buffer placement in distributed RC-tree networks for minimal Elmore delay
22. Simultaneous routing and buffer insertion with restrictions on buffer locations