Accurate estimation of global buffer delay within a floorplan

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 706-711

  Alpert, Charles J ^a   Hu, Jiang ^b   Sapatnekar, Sachin S ^c   Sze, C N ^b  

^a IBM   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

^c University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER DELAY; BUFFER INSERTION; DECOUPLING; GLOBAL ROUTING;

ALGORITHMS; APPROXIMATION THEORY; CAPACITANCE; ERROR ANALYSIS; HEURISTIC METHODS; MATHEMATICAL MODELS; OPTIMIZATION; RESOURCE ALLOCATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 16244382538     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2004.1382667     Document Type: Conference Paper

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