Placement driven synthesis case studies on two sets of two chips: Hierarchical and flat

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2004, Pages 190-197

  Osler, Peter J ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

Application Specific Integrated Circuit (ASIC); Netlist; Placement; Register Transfer Level (RTL); Static Timing Analysis (STA); Synthesis

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER AIDED ENGINEERING; CONSTRAINT THEORY; COSTS; HIERARCHICAL SYSTEMS;

NETLIST; PLACEMENT; REGISTER TRANSFER LEVEL (RTL); STATIC TIMING ANALYSIS (STA);

MICROPROCESSOR CHIPS;

EID: 2942672235     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/981066.981107     Document Type: Conference Paper

References (0)