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Volumn , Issue , 2006, Pages 308-313

Fast algorithms for slew constrained minimum cost buffering

Author keywords

Buffer insertion; Physical design; Slew constraint

Indexed keywords

ADAPTIVE CONTROL SYSTEMS; COST EFFECTIVENESS; DYNAMIC PROGRAMMING; LEARNING ALGORITHMS; PROBLEM SOLVING;

EID: 34547212972     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146990     Document Type: Conference Paper
Times cited : (21)

References (12)
  • 2
    • 2942672235 scopus 로고    scopus 로고
    • Placement driven synthesis case studies on two sets of two chips: Hierarchical and flat
    • P.J. Osler, "Placement driven synthesis case studies on two sets of two chips: hierarchical and flat," in Proceedings of the ACM International Symposium on Physical Design, pp. 190-197, 2004.
    • (2004) Proceedings of the ACM International Symposium on Physical Design , pp. 190-197
    • Osler, P.J.1
  • 3
    • 0030110490 scopus 로고    scopus 로고
    • Optimal wire sizing and buffer insertion for low power and a generalized delay model
    • J. Lillis and C-K. Cheng and T.-T.Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," IEEE Journal of Solid State Circuits, vol. 31, no. 3, pp. 437-447, 1996.
    • (1996) IEEE Journal of Solid State Circuits , vol.31 , Issue.3 , pp. 437-447
    • Lillis, J.1    Cheng, C.-K.2    Lin, T.-T.Y.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.