Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Microelectronics Reliability

Volumn 48, Issue 4, 2008, Pages 602-610

  Zhang, Xiaowu ^a   Kripesh, Vaidyanathan ^a   Chai, T C ^a   Tan, Teck Chun ^a   Pinjala, D ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COST REDUCTION; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; MOBILE COMPUTING; RELIABILITY ANALYSIS; THERMAL CYCLING; VISCOPLASTICITY;

COFFIN-MANSON EQUATION; FABRICATION COST; WAFER LEVEL PACKAGING (WLP);

SOLDERED JOINTS;

EID: 42649098594     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2007.05.009     Document Type: Article

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