Design and analysis of wafer-level CSP with a double-pad structure

IEEE Transactions on Components and Packaging Technologies

Volumn 28, Issue 1, 2005, Pages 117-126

  Lin, Ji Cheng ^a   Cheng, Hsien Chie ^b   Chiang, Kuo Ning ^c  

^a DELTA ELECTRONICS INC   (Taiwan)

^b FENG CHIA UNIVERSITY   (Taiwan)

^c NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Accelerated thermal cycling test; Finite element (FE) modeling; Solder joint reliability; Twyman Green interferometer; Wafer level packaging

Indexed keywords

FAILURE ANALYSIS; FATIGUE OF MATERIALS; FINITE ELEMENT METHOD; INTEGRATED CIRCUITS; INTERFEROMETERS; MATHEMATICAL MODELS; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; STRAIN; THERMAL CYCLING; WEIBULL DISTRIBUTION;

ACCELERATED THERMAL CYCLING TEST; FINITE ELEMENT (FE) MODELING; SOLDER JOINT RELIABILITY; TWYMAN-GREEN INTERFEROMETER; WAFER LEVEL PACKAGING;

CHIP SCALE PACKAGES;

EID: 15744399371     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAPT.2005.843216     Document Type: Article

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