Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Microelectronics Reliability

Volumn 46, Issue 12, 2006, Pages 2131-2138

  Tee, Tong Yan ^a   Ng, Hun Shen ^a   Zhong, Zhaowei ^b  

^a STMICROELECTRONICS   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COPPER COMPOUNDS; FLIP CHIP DEVICES; NONLINEAR SYSTEMS; RELIABILITY THEORY; SILVER COMPOUNDS; THERMAL CYCLING; TIN COMPOUNDS; VISCOPLASTICITY;

NON-LINEAR VISCOPLASTIC ANALYSIS; SNAGCU; STACKED DIE; WIREBOND (WB) INTERCONNECTS;

SOLDERED JOINTS;

EID: 33748938357     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2006.01.010     Document Type: Article

References (20)

1. Herard L, Baraton X, Garnier M, Boillot V. Stacked die package for mass production: an overview. In: Proceedings of 13th european microelectronics and packaging conference, 2001. p. 330-5.
2. Darveaux R., Banerji K., Mawer A., and Dody G. Reliability of plastic ball grid array assembly. In: Lau J. (Ed). Ball grid array technology (1995), McGraw-Hill, New York 379-442
3. Darveaux R. Solder joint fatigue life model. In: Proceedings of TMS annual meeting, Orlando, FL, 1997. p. 213-8.
4. Johnson Z. Implementation of and extensions to Darveaux's approach to finite-element simulation of BGA solder joint reliability. In: Proceedings of 49th electronic components and technology conference, ECTC, USA, 1999. p. 1190-5.
5. Mawer A, Vo N, Johnson Z, Lindsay W. Board-level characterization of 1.0 and 1.27 mm pitch PBGA for automotive under-hood applications. In: Proceedings of 49th electronic components and technology conference, ECTC, USA, 1999. p. 118-24.
6. Darveaux R. Effect of simulation methodology on solder joint crack growth correlation. In: Proceedings of 50th electronic components and technology conference, ECTC, Las Vegas, NE, 2000. p. 1048-58.
7. Tee TY, Sivakumar K, Do-Bento-Vieira A. Board level solder joint reliability modeling of LFBGA package. In: Proceedings of 2nd EMAP conference, Hong Kong, 2000. p. 51-4.
8. Tee T.Y., Ng H.S., Yap D., Baraton X., and Zhong Z.W. Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications. Microelectron Reliab 43 7 (2003) 1117-1123
9. Tee T.Y., Ng H.S., Yap D., and Zhong Z.W. Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages. Microelectron Reliab 43 8 (2003) 1329-1338
10. Tee T.Y., Ng H.S., Zhong Z.W., and Zhou J. Design analysis and optimization of wafer-level CSP board level solder joint reliability. J Surf Mount Technol 18 3 (2005) 26-31
11. Tee T.Y., and Zhong Z.W. Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages. Microelectron Reliab 44 12 (2004) 1957-1965
12. Ng HS, Tee TY, Pan S, Lam P. Development and application of lead-free solder joint fatigue model for CSP. In: Proceedings of 6th EMAP Conference, Malaysia, 2004. p. 442-9.
13. Ng HS, Tee TY, Goh KY, Luan JE, Reinikainen T, Hussa E, Kujala A. Absolute and relative fatigue life prediction methodology for virtual qualification and design enhancement of lead-free BGA. In: Proceedings of 55th electronic components and technology conference, ECTC, USA, 2005. p. 1282-91.
14. Lee W.W., Nguyen L.T., and Selvaduray G.S. Solder joint fatigue models: review and applicability to chip scale packages. Microelectron Reliab 40 (2000) 231-244
15. Zhong ZW, Wang M. Stacked chip size packaging. In: Proceedings of advanced packaging technology symposium, SEMICON Singapore, 2002. p. 7-11.
16. Zhong ZW, Yip PK. Study of a 3D electronics package. In: Proceedings of advanced packaging technology symposium, SEMICON Singapore, 2002. p. 61-6.
17. Schubert A, Dudek R, Walter H, Jung E, Gollhardt A, Michel B, Reichl H. Reliability assessment of flip-chip assemblies with lead-free solder joints. In: Proceedings of 52nd ECTC conference, USA, 2002. p. 1246-55.
18. Levis K, Mawer A. Assembly and solder joint reliability of plastic ball grid array with lead-free versus lead-tin interconnect. In: Proceedings of 50th ECTC conference, 2000. p. 1198-204.
19. Murty KL, Turlik I. Deformation mechanisms in lead-tin alloys, application to solder reliability in electronic packages. In: Proceedings of ASME/JSME, 1992. p. 309-18.
20. ANSYS User's Manual. Swanson analysis systems, 1994, vol. IV, p. 4.23-25.