Wafer-level chip size package (WL-CSP)

IEEE Transactions on Advanced Packaging

Volumn 23, Issue 2, 2000, Pages 233-238

  Topper, Michael ^a   Fehlberg, Simone ^a   Scherpinski, Katrin ^a   Karduck, Claudia ^a   Glaw, Veronika ^a   Heinricht, Katrin ^b   Coskina, Paradiso ^b   Ehrmann, Oswin ^b   Reichl, Herbert ^b  

^a FRAUNHOFER IZM   (Germany)

^b NOKIA   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DEPOSITION; DIELECTRIC MATERIALS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; PASSIVATION; POLYMERS; PRINTED CIRCUIT BOARDS; SILICON WAFERS; SOLDERING ALLOYS; SURFACE MOUNT TECHNOLOGY; THIN FILMS;

BALL GRID ARRAYS; BOARD TECHNOLOGY; REDISTRIBUTION TECHNOLOGY; SINGLE CHIP PACKAGE; SOLDER BALLS; WAFER LEVEL CHIP SIZE PACKAGE;

INTEGRATED CIRCUITS;

EID: 0033686294     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/6040.846640     Document Type: Article

References (13)

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