Ultra CSP™ - A wafer level package

IEEE Transactions on Advanced Packaging

Volumn 23, Issue 2, 2000, Pages 220-226

  Elenius, Peter ^a   Barrett, Scott ^a   Goodman, Thomas ^a  

^a Flip Chip Technologies   (United States)

Author keywords

Chip scale package; CSP; Ultracsp; Wafer level packaging

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; INTEGRATED CIRCUIT MANUFACTURE; PRINTED CIRCUIT BOARDS; SILICON WAFERS; THERMAL CYCLING;

BURN IN OPTIONS; CHIP SCALE PACKAGE; WAFER FAB; WAFER LEVEL PACKAGING TECHNOLOGY; WAFER LEVEL TEST;

ELECTRONICS PACKAGING;

EID: 0033718946     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/6040.846638     Document Type: Article

References (6)

1. R. Crowley, Chip-Scale Packaging: Technology Analysis and Market Forecast, Redpoint Res. Tech. Rep., Feb. 1998.
2. H. Asakura, "Wafer level CSP feature," in Nikkei Microdevices, Tokyo, Japan: Nikkei Business Publications, Feb. 1999.
3. D. H. Kim et al., "Electrical performance of a lead frame csp and a wafer level CSP for DRAM applications," in Proc. 4th Pan Pacific Microelectron. Symp., Kauai, HI, Feb. 1999, pp. 79-89.
4. D.H. Kim, private communication, Hyundai Electronics.
5. S. Popelar, "A parametric study of flip chip reliability based on solder fatigue modeling," in Proc. IEMT Conf., Austin, TX, 1997.
6. T. Wakabayashi, "Wafer level CSP user's perspective," presented at the Nikkei Microdevices Wafer Level CSP Seminar, Tokyo, Japan, Nov. 1998.