MicroSMD — A wafer level chip scale package

IEEE Transactions on Advanced Packaging

Volumn 23, Issue 2, 2000, Pages 227-232

  Kelkar, N ^a   Mathew, R ^a   Takiar, H ^a   Nguyen, L ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COATINGS; ELECTRONICS PACKAGING; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT DESIGN; RELIABILITY; SILICON WAFERS; SURFACE MOUNT TECHNOLOGY;

BUMP PITCH; PACKAGE CONSTRUCTION; PACKAGE RELIABILITY; WAFER LEVEL CHIP SCALE PACKAGE;

INTEGRATED CIRCUITS;

EID: 0033715474     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/6040.846639     Document Type: Article

References (4)

1. J. H. Lau and S. W. R. Lee, Chip Scale Package: Design, Materials, Process, Reliability, and Applications. New York: McGraw Hill, 1999.
2. "Die sized ball grid array," JEDEC Registered Outline MO-211-FXBGA.
3. Moisture/reflow sensitivity classification for plastic integrated circuit surface mount devices, J-STD-020, Oct. 1996.
4. Guidelines for accelerated reliability testing of surface mount solder attachments, IPC-5M-785, Nov. 1992.