Sea-of-Leads MEMS I/O interconnects for low-k IC packaging

Journal of Microelectromechanical Systems

Volumn 15, Issue 3, 2006, Pages 523-530

  Dang, Bing ^a   Bakir, Muhannad S ^a   Patel, Chirag S ^b   Thacker, Hiren D ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Low k interlayer dielectrics; Microelectromechanical systems (MEMS) I O interconnects; Solder joints; Underfill

Indexed keywords

DIELECTRIC MATERIALS; ELECTRONICS PACKAGING; FAILURE ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE; OPTIMIZATION; SUBSTRATES; THERMAL EXPANSION;

COEFFICIENT OF THERMAL EXPANSION (CTE); LOW-K INTERLAYER DIELECTRICS; SOLDER JOINTS; UNDERFILL; WAFER-LEVEL PACKAGING;

MICROELECTROMECHANICAL DEVICES;

EID: 33745125049     PISSN: 10577157     EISSN: None     Source Type: Journal    
DOI: 10.1109/JMEMS.2006.876792     Document Type: Article

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