Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging

IEEE Transactions on Advanced Packaging

Volumn 29, Issue 2, 2006, Pages 343-353

  Liao, E B ^a,b   Tay, Andrew A O ^a   Ang, Simon S ^a,c   Feng, H H ^b   Nagarajan, R ^b   Kripesh, V ^b  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

^c University of Arkansas   (United States)

Author keywords

Compliance; Electrical parasitic; Flip chip; Multicopper column interconnect; Wafer level packaging

Indexed keywords

COMPUTER SIMULATION; FATIGUE OF MATERIALS; FLIP CHIP DEVICES; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; WAVEGUIDES; WSI CIRCUITS;

ELECTRICAL PARASITIC; MULTI-COPPER-COLUMN INTERCONNECT; WAFER-LEVEL PACKAGING;

ELECTRONICS PACKAGING;

EID: 33646503200     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.chemosphere.2006.02.010     Document Type: Article

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