Analysis of wire interconnect technology wafer level packaging

Journal of Electronic Packaging

Volumn 124, Issue 3, 2002, Pages 234-239

  Lin, Y T ^a   Peng, C T ^a   Chiang, K N ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Chip Scale Package; Wafer Level Packaging; Wire Interconnect Technology

Indexed keywords

EID: 0041369612     PISSN: 10437398     EISSN: None     Source Type: Journal    
DOI: 10.1115/1.1481368     Document Type: Article

References (15)

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