Soft error mitigation through selective addition of functionally redundant wires

IEEE Transactions on Reliability

Volumn 57, Issue 1, 2008, Pages 23-31

  Almukhaizim, Sobeeh ^a   Makris, Yiorgos ^b  

^a KUWAIT UNIVERSITY   (Kuwait)

^b Yale University   (United States)

Author keywords

Logic implications; Single event transient; Soft error rate; Soft error sensitization probability

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; OPTIMIZATION; PROBABILITY; SUPERCONDUCTING WIRE;

LOGIC IMPLICATION; SINGLE-EVENT TRANSIENT; SOFT ERROR RATE; SOFT ERROR SENSITIZATION PROBABILITY;

NETWORKS (CIRCUITS);

EID: 41449083508     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/TR.2008.916877     Document Type: Article

References (32)

1. P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi, "Modeling the effect of technology trends on the soft error rate of combinational logic," in International Conference on Dependable Systems and Networks, 2002, pp. 389-398.
2. L. Lantz, "Tutorial: Soft errors induced by alpha particles," IEEE Trans. Reliability, vol. 45, no. 2, pp. 174-179, 1996.
3. P. Lidén, P. Dahlgren, R. Johansson, and J. Karlsson, "On latching probability of particle induced transients in combinational networks," in Symposium on Fault-Tolerant Computing, 1994, pp. 340-349.
4. K. Mohanram and N. A. Touba, "Cost-effective approach for reducing soft error failure rate in logic circuits," in International Test Conference, 2003, pp. 893-901.
5. C. Zhao, X. Bai, and S. Dey, "A scalable soft spot analysis methodology for noise effects in nano-meter circuits," in Design Automation Conference, 2004, pp. 894-899.
6. M. Zhang and N. R. Shanbhag, "A soft error rate analysis (SERA) methodology," in International Conference on Computer-Aided Design 2004, pp. 111-118.
7. S. Krishnaswamy, G. F. Viamonte, I. L. Markov, and J. P. Hayes, "Accurate reliability evaluation and enhancement via probabilistic transfer matrices," in Design, Automation and Test in Europe Conference, 2005, pp. 282-287.
8. B. Zhang, W. S. Wang, and M. Orshansky, "FASER: Fast analysis of soft error susceptibility for cell-based designs," in International Symposium on Quality Electronic Design, 2006, pp. 755-760.
9. N. Miskov-Zivanov and D. Marculescu, "Circuit reliability analysis using symbolic techniques," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 25, pp. 2638-2649, 2006.
10. J. M. Cazeaux, D. Rossi, M. Omana, C. Metra, and A. Chatterjee, "On transistor level gate sizing for increased robustness to transient faults," in International On-Line Testing Symposium, 2005, pp. 23-28.
11. Y. S. Dhillon, A. U. Diril, and A. Chatterjee, "Soft-error tolerance analysis and optimization of nanometer circuits," in Design, Automation and Test in Europe Conference, 2005, pp. 288-293.
12. N. Miskov-Zivanov and D. Marculescu, "MARS-C: Modeling and reduction of soft errors in combinational circuits," in Design Automation Conference, 2006, pp. 767-772.
13. Q. Zhou and K. Mohanram, "Gate sizing to radiation harden combinational logic," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 1, pp. 155-166, 2006.
14. T. Monnier, F. M. Roche, J. Cosculluela, and R. Velazco, "SEU testing of a novel hardened register implemented using standard CMOS technology," IEEE Trans. Nuclear Science, vol. 46, no. 6, pp. 1440-1444, 1999.
15. M. Omana, D. Rossi, and C. Metra, "Novel transient fault hardened static latch," in International Test Conference, 2003, pp. 886-892.
16. M. Nicolaidis, "Time redundancy based soft-error tolerance to rescue nanometer technologies," in VLSI Test Symposium, 1999, pp. 86-94.
17. P. Elakkumanan, K. Prasad, and R. Sridhar, "Low power SER tolerant design to mitigate single event transients in nanoscale circuits," ASP Journal of Low Power Electronics, vol. 1, pp. 182-193, 2005.
18. V. Joshi, R. Rao, D. Sylvester, and D. Blaauw, "Logic SER reduction through flip-flop redesign," in International Symposium on Quality Electronic Design, 2006, pp. 611-616.
19. D. G. Mavis and P. H. Eaton, "Soft error rate mitigation techniques for modern microcircuits," in International Reliability Physics Symposium, 2002, pp. 216-225.
20. S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim, "Robust system design with built-in soft-error resilience," IEEE Computer, vol. 38, no. 2, pp. 43-52, 2005.
21. P. Elakkumanan, K. Prasad, and R. Sridhar, "Time redundancy based scan flip-flop reuse to reduce SER of combinational logic," in International Symposium on Quality of Electronic Design, 2006, pp. 617-624.
22. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. :KLuwer Academic Publishers, 2000.
23. H. Fujiwara and T. Shimono, "On the acceleration of test generation algorithms," IEEE Trans. Computers, vol. 32, no. 12, pp. 1137-1144, 1983.
24. M. Schulz, E. Trischler, and T. Sarfert, "SOCRATES: A highly efficient automatic test pattern generation system," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 1, pp. 126-137, 1988.
25. M. Schulz and E. Auth, "Improved deterministic test pattern generation with applications to redundancy identification," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 7, pp. 811-816, 1989.
26. W. Kunz and D. K. Pradhan, "Accelerated dynamic learning for test generation in combinational circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 5, pp. 684-694, 1993.
27. W. Kunz and D. K. Pradhan, "Recursive learning: A new implication technique for efficient solutions to CAD-problems: Test, verification and optimization," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 9, pp. 1149-1158, 1994.
28. J. Zhao, E. Rudnick, and J. Patel, "Static logic implication with application to fast redundancy identification," in VLSI Test Symposium, 1997, pp. 288-293.
29. W. Kunz, D. Stoffel, and P. R. Menon, "Logic optimization and equivalence checking by implication analysis," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 3, pp. 1149-1158, 1997.
30. ISCAS'89 Benchmark Circuits Information [Online]. Available: http:// www.cbl.ncsu.edu
31. H. K. Lee and D. S. Ha, "HOPE: An efficient parallel fault simulator for synchronous sequential circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 9, pp. 1048-1058, 1996.
32. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldahna, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis," EECS UC Berkeley, CA 94720, ERL MEMO. No. UCB/ERL M92/41, 1992.