Logic optimization and equivalence checking by implication analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 3, 1997, Pages 266-281

  Kunz, Wolfgang ^a   Stoffel, Dominik ^b   Menon, Prem R ^a  

^a UNIVERSITY OF POTSDAM   (Germany)

^b University of Massachusetts   (United States)

Author keywords

ATPG; Implication analysis; Logic synthesis; Logic verification; Miter; Permissible function; Recursive learning; Redundancy elimination; Transduction

Indexed keywords

BOOLEAN ALGEBRA; COMPUTER AIDED LOGIC DESIGN; HEURISTIC METHODS; LEARNING SYSTEMS; OPTIMIZATION; RECURSIVE FUNCTIONS;

AUTOMATIC TEST PATTERN GENERATION (ATPG); LOGIC VERIFICATION; MULTILEVEL LOGIC OPTIMIZATION;

COMBINATORIAL CIRCUITS;

EID: 0031097753     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.594832     Document Type: Article

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