Static logic implication with application to redundancy identification

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1997, Pages 288-293

  Zhao, Jian Kun ^a   Rudnick, Elizabeth M ^a   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGEBRA; ALGORITHMS; COMBINATORIAL CIRCUITS; ITERATIVE METHODS; REDUNDANCY;

STATIC LOGIC IMPLICATION;

COMPUTER AIDED LOGIC DESIGN;

EID: 0030686639     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)