SEU testing of a Novel hardened register implemented using standard CMOS technology

IEEE Transactions on Nuclear Science

Volumn 46, Issue 6 PART 1, 1999, Pages 1440-1444

  Monnier, T ^a   Roche, P M ^a   Cosculluela, J ^a   Velazco, R ^a  

^a TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; HEAVY IONS; INTEGRATED CIRCUIT TESTING; PERTURBATION TECHNIQUES; SHIFT REGISTERS;

MEMORY STRUCTURE; POWER CONSUMPTION; SINGLE EVENT UPSET;

RADIATION HARDENING;

EID: 0033306968     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.819105     Document Type: Article

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