MARS-C: Modeling and reduction of soft errors in combinational circuits

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 767-772

  Miskov Zivanov, Natasa ^a   Marculescu, Diana ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Reliability symbolic techniques; SER

Indexed keywords

CIRCUIT SIMULATION; ERROR CORRECTION; GATES (TRANSISTOR); NANOELECTRONICS; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

ERROR SUSCEPTIBILITY; RELIABILITY SYMBOLIC TECHNIQUES; SOFT ERROR RATE (SER); THRESHOLD VALUES;

COMBINATORIAL CIRCUITS;

EID: 33847715275     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147104     Document Type: Conference Paper

References (18)

1. K. Mohanram and N. A. Touba. Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. In Proc. of International Test Conference (ITC), pp. 893-901, 2003.
2. R. C. Baumann. Soft Errors in Advanced Computer Systems. In IEEE Design and Test of Computers, Vol. 22, Issue 3, 2005.
3. R. E. Bryant. Graph-Based Algorithms for Boolean Function Manipulation. In IEEE Transaction on Computers, C-35-8, pp. 677-691, August 1986.
4. R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, F. Somenzi. Algebraic Decision Diagrams and Their Applications. In Proc. of ACM/IEEE International Conference on Computer Aided Design (ICCAD), pp. 188-191, November 1993.
5. C. Zhao, X. Bai, and S. Dey. A Scalable Soft Spot Analysis Methodology for Noise Effects in Nano-meter Circuits. In Proc. of ACM/IEEE Design Automation Conference (DAC), pp. 894-899, June 2004.
6. M. Zhang and N. R. Shanbhag. A Soft Error rate Analysis (SERA) Methodology. In Proc. of ACM/IEEE International Conference on Computer Aided Design (ICCAD), pp. 111-118, 2004.
7. Y. S. Dhillon, A. U. Diril, and A. Chatterjee. Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits. In Proc. of Design, Automation and Test in Europe (DATE), pp. 288-293, March 2005.
8. S. Krishnaswamy, G. F. Viamonte, I. L. Markov, and J. P. Hayes. Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices. In Proc. of Design, Automation and Test in Europe (DATE), pp. 282-287, March 2005.
9. th IEEE International On-Line Testing Symposium, IOLTS'03, pp. 11-115, July 2003.
10. B. Zhang, W. Wang, and M. Orshansky. FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. In Proc. of International Symposium on Quality Electronic Design (ISQED), March 2006.
11. P. Liden, P. Dahlgren, R. Johansson, and J. Karlsson. On Latching Probability of Particle Induced Transients in Combinational Networks. In Proc. of Fault-Tolerant Computing Symposium, pp. 340-349, 1994.
12. M. P. Baze and S. P. Buehner. Attenuation of Single Event Induced Puises in CMOS Combinational Logic. In IEEE Transaction on Nuclear Science, Vol. 44, No. 6, pp. 2217-2223, December 1997.
13. D. Marculescu, R. Marculescu, and M. Pedram. Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation. In Proc. of IEEE Design, Automation and Test in Europe Conf. (DATE), February 1998.
14. J. M. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits. Prentice Hall, 2003.
15. Q. Zhou and K. Mohanram. Cost-Effective Radiation Hardening Technique for Combinational Logic. In Proc. of International Conference on Computer-Aided Design (ICCAD), pp. 100-106, November 2004.
16. Berkeley Predictive Technology Model (BPTM): http://www-device. eecs.berkeley.edu/~ptm.
17. I. Sutherland,B. Sproull and D. Harris. Logical Effort: Designing FastCMOS Circuits. Morgan Kaufmann Publishers, Inc., pp.5-15, 63-73, 1999.
18. N. Miskov-Zivanov and D. Marculescu. Circuit Reliability Analysis Using Symbolic Techniques.To appear in IEEE Transactions on Computer Aided Design (TCAD), 2006.