On transistor level gate sizing for increased robustness to transient faults

Proceedings - 11th IEEE International On-Line Testing Symposium, IOLTS 2005

Volumn 2005, Issue , 2005, Pages 23-28

  Cazeaux, J M ^a   Rossi, D ^a   Omana M ^a   Metra, C ^a   Chatterjee, A ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT NODE; CRITICAL CHARGE; ELECTRICAL LEVEL SIMULATIONS; TRANSIENT FAULT (TF);

ELECTRIC CONDUCTANCE; ERROR DETECTION; NETWORKS (CIRCUITS); ROBUSTNESS (CONTROL SYSTEMS); TRANSIENTS;

GATES (TRANSISTOR);

EID: 33745485468     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2005.49     Document Type: Conference Paper

References (13)

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