Architecture approaching the atomic scale

ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference

Volumn 2007, Issue , 2007, Pages 11-20

  DeHon, André ^a  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; INTEGRATED CIRCUITS; LITHOGRAPHY; LOGIC CIRCUITS;

BOTTOM-UP TECHNIQUES; COMPUTING ARCHITECTURES; LITHOGRAPHIC SCALING; TOP-DOWN TECHNIQUES;

SOLID STATE DEVICES;

EID: 39549085127     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2007.4430874     Document Type: Conference Paper

References (60)

1. A. M. Morales and C. M. Lieber, "A laser ablation method for synthesis of crystalline semiconductor nanowires," Science, vol. 279, pp. 208-211, 1998.
2. Y. Cui, L. J. Lauhon, M. S. Gudiksen, J. Wang, and C. M. Lieber, "Diameter-controlled synthesis of single crystal silicon nanowires," Applied Physics Letters, vol. 78, no. 15, pp. 2214-2216, 2001.
3. Y. Wu and P. Yang, "Germanium Nanowire Growth via Simple Vapor Transport," Chemistry of Materials, vol. 12, pp. 605-607, 2000.
4. P. V. Radovanovic, C. J. Barrelet, S. Gradecak, F. Qian, and C. M. Lieber, "General syntehsis of manganese-doped II-VI and III-V semiconductor nanowires," Nanoletters, vol. 5, no. 7, pp. 1407-1411, 2005.
5. C. J. Barrelet, Y. Wu, D. C. Bell, and C. M. Lieber, "Synthesis of CdS and ZnS nanowires using single-source molecular precursors," Journal of the American Chemical Society, vol. 125, no. 38, pp. 11498-11499, 2003.
6. Y. Wu, Y. Cui, L. Huynh, C. J. Barrelet, D. C. Bell, and C. M. Lieber, "Controlled growth and structures of molecular-scale silicon nanowires," Nanoletters, vol. 4, no. 3, pp. 433-436, 2004.
7. M. S. Gudiksen, J. Wang, and C. M. Lieber, "Synthetic control of the diameter and length of semiconductor nanowires," Journal of Physical Chemistry B, vol. 105, pp. 4062-4064, 2001.
8. B. Zheng, Y. Wu, P. Yang, and J. Liu, "Synthesis of ultra-long and highly-oriented silicon oxide nanowires from alloy liquid," Advanced Materials, vol. 14, p. 122, 2002.
9. Y. Tan, X. Dai, Y. Li, and D. Zhu, "Preparation of gold, platinum, palladium and silver nanoparticles by the reduction of their salts with a weak reductant-potassium bitartrate," Journal of Material Chemistry, vol. 13, pp. 1069-1075, 2003.
10. Y. Huang, X. Duan, Y. Cui, L. Lauhon, K. Kim, and C. M. Lieber, "Logic gates and computation from assembled nanowire building blocks," Science, vol. 294, pp. 1313-1317, November 9 2001.
11. Y. Wu, J. Xiang, C. Yang, W. Lu, and C. M. Lieber, "Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures," Nature, vol. 430, pp. 61-64, July 1 2004.
12. M. S. Gudiksen, L. J. Lauhon, J. Wang, D. C. Smith, and C. M. Lieber, "Growth of nanowire superlattice structures for nanoscale photonics and electronics," Nature, vol. 415, pp. 617-620, February 7 2002.
13. Y. Wu, R. Fan, and P. Yang, "Block-by-block growth of single-crystalline Si/SiGe superlattice nanowires," Nanoletters, vol. 2, no. 2, pp. 83-86, February 2002.
14. M. T. Björk, B. J. Ohlsson, T. Sass, A. I. Persson, C. Thelander, M. H. Magnusson, K. Depper, L. R. Wallenberg, and L. Samuelson, "One-dimensional steeplechase for electrons realized," Nanoletters, vol. 2, no. 2, pp. 87-89, February 2002.
15. L. J. Lauhon, M. S. Gudiksen, D. Wang, and C. M. Lieber, "Epitaxial core-shell and core-multi-shell nanowire heterostructures," Nature, vol. 420, pp. 57-61, 2002.
16. M. Law, J. Goldberger, and P. Yang, "Semiconductor nanowires and nanotubes," Annual Review Material Science, vol. 34, pp. 83-122, August 2004.
17. M. Ritala, "Advanced ALE processes of amorphous and polycrystalline films," Applied Surface Science, vol. 112, pp. 223-230, 1997.
18. M. Ritala, K. Kukli, A. Rahtu, P. I. Räisänen, M. Leskelä, T. Sajavaara, and J. Keinonen, "Atomic layer deposition of oxide thin films with metal alkoxides as oxygen sources," Science, vol. 288, pp. 319-321, April 14 2000.
19. C. Yang, Z. Zhong, and C. M. Lieber, "Encoding electronic properties by synthesis of axial modulation-doped silicon nanowires," Science, vol. 310, pp. 1304-1307, November 25 2005.
20. Y. Huang, X. Duan, Q. Wei, and C. M. Lieber, "Directed assembly of one-dimensional nanostructures into functional networks," Science, vol. 291, pp. 630-633, January 26 2001.
21. D. Whang, S. Jin, and C. M. Lieber, "Nanolithography using hierarchically assembled nanowire masks," Nanoletters, vol. 3, no. 7, pp. 951-954, July 9 2003.
22. N. A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P. M. Petroff, and J. R. Heath, "Ultrahigh-density nanowire lattices and circuits," Science, vol. 300, pp. 112-115, April 4 2003.
23. M. D. Austin, H. Ge, W. Wu, M. Li, Z. Yu, D. Wasserman, S. A. Lyon, and S. Y. Chou, "Fabrication of 5 nm linewidth and 14 nm pitch features by nanoimprint lithography," Applied Physics Letters, vol. 84, no. 26, pp. 5299-5301, June 28 2004.
24. Z. Yu, W. Wu, G.-Y. Jung, D. L. Olynick, J. Straznicky, X. Li, Z. Li, W. M. Tong, A. Liddle, S.-Y. Wang, and R. S. Williams, "Fabrication of 30 nm pitch imprint moulds by frequency doubling for nanowire arrays," Nanotechnology, vol. 17, pp. 4956-4961, 2006.
25. S. R. J. Brueck, International Trends in Applied Optics. Bellingham, WA: SPIE Press, 2002, ch. 5: There are No Fundamental Limits to Optical Lithography, pp. 85-109.
26. Y. Chen, D. A. A. Ohlberg, X. Li, D. R. Stewart, R. S. Williams, J. O. Jeppesen, K. A. Nielsen, J. F. Stoddart, D. L. Olynick, and E. Anderson, "Nanoscale molecular-switch devices fabricated by imprint lithography," Applied Physics Letters, vol. 82, no. 10, pp. 1610-1612, 2003.
27. Y. Chen, G.-Y. Jung, D. A. A. Ohlberg, X. Li, D. R. Stewart, J. O. Jeppesen, K. A. Nielsen, J. F. Stoddart, and R. S. Williams, "Nanoscale molecular-switch crossbar circuits," Nanotechnology, vol. 14, pp. 462-468, 2003.
28. C. Collier, G. Mattersteig, E. Wong, Y. Luo, K. Beverly, J. Sampaio, F. Raymo, J. Stoddart, and J. Heath, "A [2]Catenane-Based Solid State Reconfigurable Switch," Science, vol. 289, pp. 1172-1175, 2000.
29. C. L. Brown, U. Jonas, J. A. Preece, H. Ringsdorf, M. Seitz, and J. F. Stoddart, "Introduction of [2]catenanes into langmuir films and langmuir-blodgett multilayers, a possible strategy for molecular information storage materials," Langmuir, vol. 16, no. 4, pp. 1924-1930, 2000.
30. D. R. Stewart, D. A. A. Ohlberg, P. A. Beck, Y. Chen, R. S. Williams, J. O. Jeppesen, K. A. Nielsen, and J. F. Stoddart, "Molecule-independent electrical switching in pt/organic monolayer/ti devices," Nanoletters, vol. 4, no. 1, pp. 133-136, 2004.
31. Z. Fan, X. Mo, C. Lou, Y. Yao, D. Wang, G. Chen, and J. G. Lu, "Structures and electrical properties for ag-tetracyanoquinodimetheane organometallic nanowires," IEEE Transactions on Nanotechnology, vol. 4, no. 2, pp. 238-241, March 2005.
32. J. Brault, M. Saitoh, and T. Hiramoto, "Channel width and length dependence si nanocrystal memories with ultra-nanoscale channel," IEEE Transactions on Nanotechnology, vol. 4, no. 3, pp. 349-354, 2005.
33. S. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walsta, and C. Dai, "Impact of CMOS process scaling and SOI on the soft error rates of logic processes," in Proceedings of Symposium on VLSI Digest of Technology Papers, 2001, pp. 73-74.
34. L. B. Kish, "End of moores law: Thermal (noise) death of integration in micro and nano electronics," Physics Letters A, vol. 305, pp. 144-149, 2002.
35. J. Kim and L. Kish, "Error rate in current-controled logic processors with shot noise," Fluctuation and Noise Letters, vol. 4, no. 1, pp. 83-86, 2004.
36. D. K. Schroder and J. A. Babcock, "Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing," Journal of Applied Physics, vol. 94, no. 1, pp. 1-18, July 2003.
37. S.-H. Renn, C. Raynaud, J.-L. Pelloie, and F. Balestra, "A thorough investigation of the degradation induced by hot-carrier injection in deep submicron n- and p-channel partially and fully depleted unibond and SIMOX MOSFETs," IEEE Transactions on Electron Devices, vol. 45, no. 10, pp. 2146-2152, October 1998.
38. J. Osborn, R. Lacoe, D. Mayer, and G. Yabiku, "Total dose hardness of three commercial CMOS microelectronics foundries," in Proceedings of the European Conference on Radiation and Its Effects on Components and Systems, 1997, pp. 265-270.
39. A. DeHon, "Nanowire-Based Programmable Architectures," ACM Journal on Emerging Technologies in Computing Systems, vol. 1, no. 2, pp. 109-162, 2005.
40. J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, "A defect-tolerant computer architecture: Opportunities for nanotechnology," Science, vol. 280, no. 5370, pp. 1716-1721, June 12 1998.
41. Y. Luo, P. Collier, J. O. Jeppesen, K. A. Nielsen, E. Delonno, G. Ho, J. Perkins, H.-R. Tseng, T. Yamamoto, J. F. Stoddart, and J. R. Heath, "Two-dimensional molecular electronics circuits," ChemPhysChem, vol. 3, no. 6, pp. 519-525, 2002.
42. S. C. Goldstein and M. Budiu, "NanoFabrics: Spatial Computing Using Molecular Electronics," in Proceedings of the International Symposium on Computer Architecture, June 2001, pp. 178-189.
43. S. C. Goldstein and D. Rosewater, "Digital logic using molecular electronics," in ISSCC Digest of Technical Papers. IEEE, February 2002, pp. 204-205.
44. G. Snider, P. Kuekes, and R. S. Williams, "Cmos-like logic in defective, nanoscale crossbars," Nanotechnology, vol. 15, pp. 881-891, June 2004.
45. D. B. Strukov and K. K. Likharev, "CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices," Nanotechnology, vol. 16, no. 6, pp. 888-900, June 2005.
46. G. S. Snider and R. S. Williams, "Nano/CMOS architetures using a field-programmable nanowire interconnect," Nanotechnology, vol. 18, no. 3, January 2007.
47. A. DeHon, "Array-Based Architecture for FET-based, Nanoscale Electronics," IEEE Transactions on Nanotechnology, vol. 2, no. 1, pp. 23-32, March 2003.
48. A. DeHon, P. Lincoln, and J. Savage, "Stochastic Assembly of Sublithographic Nanoscale Interfaces," IEEE Transactions on Nanotechnology, vol. 2, no. 3, pp. 165-174, 2003.
49. S. Williams and P. Kuekes, "Demultiplexer for a molecular wire crossbar network," United States Patent Number: 6,256,767, July 3 2001.
50. E. Rachlin and J. E. Savage, "Nanowire addressing with randomized-contact decoders," in Proceedings of the International Conference on Computer-Aided Design, November 2006, pp. 735-742.
51. J. E. Savage, E. Rachlin, A. DeHon, C. M. Lieber, and Y. Wu, "Radial Addressing of Nanowires," ACM Journal on Emerging Technologies in Computing Systems, vol. 2, no. 2, pp. 129-154, April 2006.
52. A. DeHon, "Law of large numbers system design," in Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, S. K. Shukla and R. I. Bahar, Eds. Boston: Kluwer Academic Publishers, 2004, ch. 7, pp. 213-241.
53. A. DeHon and H. Naeimi, "Seven Strategies for Tolerating Highly Defective Fabrication," IEEE Design and Test of Computers, vol. 22, no. 4, pp. 306-315, July-August 2005.
54. A. DeHon, "Design of Programmable Interconnect for Sublithographic Programmable Logic Arrays," in Proceedings of the International Symposium on Field-Programmable Gate Arrays, February 2005, pp. 127-137.
55. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs. 101 Philip Drive, Assinippi Park, Norwell, Massachusetts, 02061 USA: Kluwer Academic Publishers, 1999.
56. H. Naeimi and A. DeHon, "A Greedy Algorithm for Tolerating Defective Crosspoints in NanoPLA Design," in Proceedings of the International Conference on Field-Programmable Technology. IEEE, December 2004, pp. 49-56.
57. V. Betz and J. Rose, "FPGA Place-and-Route Challenge," 〈http://www. eecg.toronto.edu/~vaughn/challenge/challenge.html〉, 1999.
58. S. Mitra and E. J. McCluskey, "Which concurrent error detection scheme to choose?" in Proceedings of the International Test Conference, 2000, pp. 985-994.
59. C. Mead and L. Conway, Introduction to VLSI Systems. Addison-Wesley, 1980.
60. "International technology roadmap for semiconductors," 〈http://www. itrs.net/Links/2005ITRS/Home2005.htm〉, 2005.