-
1
-
-
0000298224
-
A silicon nanocrystals based memory
-
Mar.
-
S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbé, and K. Chan, "A silicon nanocrystals based memory," Appl. Phys. Lett., vol. 68, no. 10, pp. 1377-1379, Mar. 1996.
-
(1996)
Appl. Phys. Lett.
, vol.68
, Issue.10
, pp. 1377-1379
-
-
Tiwari, S.1
Rana, F.2
Hanafi, H.3
Hartstein, A.4
Crabbé, E.F.5
Chan, K.6
-
2
-
-
0030241362
-
Fast and long retention-time nano-crystal memory
-
Sep.
-
H. I. Hanafi, S. Tiwari, and I. Khan, "Fast and long retention-time nano-crystal memory," IEEE Trans. Electron Devices, vol. 43, no. 9, pp. 1553-1558, Sep. 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, Issue.9
, pp. 1553-1558
-
-
Hanafi, H.I.1
Tiwari, S.2
Khan, I.3
-
3
-
-
0001182140
-
Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals
-
Aug.
-
Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, "Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals," J. Appl. Phys., vol. 84, no. 4, pp. 2358-2360, Aug. 1998.
-
(1998)
J. Appl. Phys.
, vol.84
, Issue.4
, pp. 2358-2360
-
-
Shi, Y.1
Saito, K.2
Ishikuro, H.3
Hiramoto, T.4
-
4
-
-
0041409629
-
2 tunneling dielectrics
-
Sep.
-
2 tunneling dielectrics," IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1823-1829, Sep. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.9
, pp. 1823-1829
-
-
Kim, D.-W.1
Kim, T.2
Banerjee, S.K.3
-
5
-
-
0142009683
-
2 high-κ tunneling dielectric
-
Oct.
-
2 high-κ tunneling dielectric," IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2067-2072, Oct. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.10
, pp. 2067-2072
-
-
Lee, J.J.1
Wang, X.2
Bai, W.3
Lu, N.4
Kwong, D.-L.5
-
6
-
-
0033350529
-
Room temperature single electron effects in a Si nano-crystal memory
-
Dec.
-
I. Kim, S. Han, K. Han, J. Lee, and H. Shin, "Room temperature single electron effects in a Si nano-crystal memory," IEEE Electron Device Lett., vol. 20, no. 12, pp. 630-631, Dec. 1999.
-
(1999)
IEEE Electron Device Lett.
, vol.20
, Issue.12
, pp. 630-631
-
-
Kim, I.1
Han, S.2
Han, K.3
Lee, J.4
Shin, H.5
-
7
-
-
0038465982
-
Growth of Si nanocrystals on alumina and integration in memory devices
-
June
-
T. Baron, A. Femandes, J.-F. Damlencourt, B. De Salvo, F. Martin, F. Mazen, and S. Haukka, "Growth of Si nanocrystals on alumina and integration in memory devices," Appl. Phys. Lett., vol. 82, no. 23, pp. 4151-4153, June 2003.
-
(2003)
Appl. Phys. Lett.
, vol.82
, Issue.23
, pp. 4151-4153
-
-
Baron, T.1
Femandes, A.2
Damlencourt, J.-F.3
De Salvo, B.4
Martin, F.5
Mazen, F.6
Haukka, S.7
-
8
-
-
0037451308
-
Large memory window and long charge-retention time in ultranarrow-channel silicon floating-dot memory
-
Mar.
-
M. Saitoh, E. Nagata, and T. Hiramoto, "Large memory window and long charge-retention time in ultranarrow-channel silicon floating-dot memory," Appl. Phys. Lett., vol. 82, no. 11, pp. 1787-1789, Mar. 2003.
-
(2003)
Appl. Phys. Lett.
, vol.82
, Issue.11
, pp. 1787-1789
-
-
Saitoh, M.1
Nagata, E.2
Hiramoto, T.3
-
9
-
-
0034246556
-
Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET's
-
Aug.
-
H. Majima, H. Ishikuro, and T. Hiramoto, "Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET's," IEEE Electron Device Lett., vol. 21, no. 8, pp. 396-398, Aug. 2000.
-
(2000)
IEEE Electron Device Lett.
, vol.21
, Issue.8
, pp. 396-398
-
-
Majima, H.1
Ishikuro, H.2
Hiramoto, T.3
-
10
-
-
2442431101
-
Large coulomb blockade oscillations at room temperature in ultranarrow wire channel MOSFET's formed by slight oxidation process
-
Dec.
-
M. Saitoh, T. Murakami, and T. Hiramoto, "Large coulomb blockade oscillations at room temperature in ultranarrow wire channel MOSFET's formed by slight oxidation process," IEEE Trans. Nanotechnol., vol. 2, no. 4, pp. 241-245, Dec. 2003.
-
(2003)
IEEE Trans. Nanotechnol.
, vol.2
, Issue.4
, pp. 241-245
-
-
Saitoh, M.1
Murakami, T.2
Hiramoto, T.3
-
11
-
-
0036923299
-
Effects of ultra-narrow channel on characteristics of MOSFET memory with silicon nanocrystal floating gates
-
San Francisco, CA, Dec.
-
M. Saitoh, E. Nagata, and T. Hiramoto, "Effects of ultra-narrow channel on characteristics of MOSFET memory with silicon nanocrystal floating gates," in Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, Dec. 2002, pp. 181-184.
-
(2002)
Int. Electron Devices Meeting Tech. Dig.
, pp. 181-184
-
-
Saitoh, M.1
Nagata, E.2
Hiramoto, T.3
-
12
-
-
2342447280
-
Single electron effects and structural effects in ultrascaled silicon nanocrystal floating-gate memories
-
Mar.
-
G. Molas, B. De Salvo, G. Ghibaudo, D. Mariolle, A. Toffoli, N. Buffet, R. Puglisi, S. Lombardo, and S. Deleonibus, "Single electron effects and structural effects in ultrascaled silicon nanocrystal floating-gate memories," IEEE Trans. Nanotechnol., vol. 3, no. 1, pp. 42-48, Mar. 2004.
-
(2004)
IEEE Trans. Nanotechnol.
, vol.3
, Issue.1
, pp. 42-48
-
-
Molas, G.1
De Salvo, B.2
Ghibaudo, G.3
Mariolle, D.4
Toffoli, A.5
Buffet, N.6
Puglisi, R.7
Lombardo, S.8
Deleonibus, S.9
-
13
-
-
0842331301
-
Room temperature operation of highly functional single-electron transistor logic based on quantum mechanical effect in ultra-small silicon dot
-
San Francisco, CA, Dec.
-
M. Saitoh and T. Hiramoto, "Room temperature operation of highly functional single-electron transistor logic based on quantum mechanical effect in ultra-small silicon dot," in Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, Dec. 2003, pp. 753-756.
-
(2003)
Int. Electron Devices Meeting Tech. Dig.
, pp. 753-756
-
-
Saitoh, M.1
Hiramoto, T.2
-
14
-
-
22244482198
-
Silicon single-electron quantum-dot transistor switch operating at room temperature
-
Mar.
-
L. Zhuang, L. Guo, and Y. Chou, "Silicon single-electron quantum-dot transistor switch operating at room temperature," Appl. Phys. Lett., vol. 72, p. 1205, Mar. 1998.
-
(1998)
Appl. Phys. Lett.
, vol.72
, pp. 1205
-
-
Zhuang, L.1
Guo, L.2
Chou, Y.3
-
15
-
-
0033116234
-
Single-electron memory for giga-to-tera bit storage
-
Apr.
-
K. Yano, T. Ishii, T. Sano, T. Mine, F. Murai, T. Hashimoto, T. Kobayashi, T. Kure, and K. Seki, "Single-electron memory for giga-to-tera bit storage," Proc. IEEE, vol. 87, no. 4, pp. 633-651, Apr. 1999.
-
(1999)
Proc. IEEE
, vol.87
, Issue.4
, pp. 633-651
-
-
Yano, K.1
Ishii, T.2
Sano, T.3
Mine, T.4
Murai, F.5
Hashimoto, T.6
Kobayashi, T.7
Kure, T.8
Seki, K.9
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