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Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2005, Issue , 2005, Pages 231-242

Dual-core execution: Building a highly scalable single-thread instruction window

(1) Zhou, Huiyang a

a University of Central Florida (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BACK PROCESSOR; CACHE-MISSING LOADS; EXECUTION PARADIGM; MULTI-CORE PROCESSORS;

BUFFER STORAGE; CHIP SCALE PACKAGES; DATA PROCESSING; MULTIPROCESSING PROGRAMS; QUEUEING NETWORKS;

MICROPROCESSOR CHIPS;

EID: 33644919336 PISSN: 1089795X EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (74)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.