-
1
-
-
0012527549
-
A dynamic multithreading processor
-
Nov.
-
H. Akkary and M. Driscoll. A Dynamic Multithreading Processor. Micro-31, Nov. 1998.
-
(1998)
Micro-31
-
-
Akkary, H.1
Driscoll, M.2
-
2
-
-
0002396593
-
DIVA: A reliable substrate for deep submicron microarchitecture design
-
Nov.
-
T. Austin. DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. Micro-32, Nov. 1999.
-
(1999)
Micro-32
-
-
Austin, T.1
-
4
-
-
0003465202
-
-
Technical Report CS-TR-1997-1342, Computer Sciences Department, University of Wisconsin-Madison
-
D. Burger and T. Austin. The SimpleScalar Tool Set, Version 2. 0. Technical Report CS-TR-1997-1342, Computer Sciences Department, University of Wisconsin-Madison, 1997.
-
(1997)
The SimpleScalar Tool Set, Version 2. 0
-
-
Burger, D.1
Austin, T.2
-
6
-
-
0033689702
-
Architectural support for scalable speculative parallelization in shared-memory systems
-
June
-
M. Cintra, J. Martinez, and J. Torrellas. Architectural Support for Scalable Speculative Parallelization in Shared-Memory Systems. ISCA-27, June 2000.
-
(2000)
ISCA-27
-
-
Cintra, M.1
Martinez, J.2
Torrellas, J.3
-
7
-
-
0034839033
-
Speculative precomputation: Long-range prefetching of delinquent loads
-
July
-
J. Collins, et al. Speculative precomputation: Long-range prefetching of delinquent loads. ISCA-28, July 2001.
-
(2001)
ISCA-28
-
-
Collins, J.1
-
9
-
-
84949037103
-
Performance characterization of a hardware framework for dynamic optimization
-
Dec.
-
B. Fans, el al. Performance Characterization of a Hardware Framework for Dynamic Optimization. Micro-34, Dec. 2001.
-
(2001)
Micro-34
-
-
Fans, B.1
-
10
-
-
0019596071
-
Trace scheduling: A technique for global microcode compaction
-
J. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers, 30(7):478-490, 1981.
-
(1981)
IEEE Transactions on Computers
, vol.30
, Issue.7
, pp. 478-490
-
-
Fisher, J.1
-
11
-
-
84988787288
-
Dynamic memory disambiguation using the memory conflict buffer
-
Oct.
-
D. Gallagher, et al. Dynamic memory disambiguation using the memory conflict buffer. ASPLOS-6, Oct. 1994.
-
(1994)
ASPLOS-6
-
-
Gallagher, D.1
-
12
-
-
0031605470
-
Data speculation support for a chip multiprocessor
-
Oct.
-
L. Hammond, M. Willey, and K. Ohikotun. Data Speculation Support for a Chip Multiprocessor. ASPLOS-8, Oct. 1998.
-
(1998)
ASPLOS-8
-
-
Hammond, L.1
Willey, M.2
Ohikotun, K.3
-
13
-
-
0027595384
-
The superblock: An effective technique for vliw and superscalar compilation
-
Mar
-
W. M. Hwu, et al. The Superblock: An Effective Technique for VLIW and Superscalar Compilation. Journal of Super-computing, 7(l):229-248, Mar 1993.
-
(1993)
Journal of Super-computing
, vol.7
, Issue.1
, pp. 229-248
-
-
Hwu, W.M.1
-
14
-
-
0032639289
-
The alpha 21264 microprocessor
-
March/April
-
R Kessler. The Alpha 21264 Microprocessor. IEEE Micro, 19(2):4-36, March/April 1999.
-
(1999)
IEEE Micro
, vol.19
, Issue.2
, pp. 4-36
-
-
Kessler, R.1
-
15
-
-
0033349998
-
Value prediction for speculative multithreaded architectures
-
Nov.
-
P. Marcuello, J. Tubella, and A. Gonzalez. Value Prediction for Speculative Multithreaded Architectures. Micro-32, Nov. 1999.
-
(1999)
Micro-32
-
-
Marcuello, P.1
Tubella, J.2
Gonzalez, A.3
-
16
-
-
0033361788
-
In search of speculative thread-level parallelism
-
Oct
-
J. Oplinger, D. Heine, and M. Lam. In Search of Speculative Thread-Level Parallelism. PACT, Oct 1999.
-
(1999)
PACT
-
-
Oplinger, J.1
Heine, D.2
Lam, M.3
-
17
-
-
0009484280
-
Trace processors
-
Dec.
-
E. Rotenberg, et al. Trace Processors. Micro-30, Dec. 1997.
-
(1997)
Micro-30
-
-
Rotenberg, E.1
-
18
-
-
84949037104
-
Speculative data-driven multi-threading
-
Jan.
-
A. Rom and G. Sohi. Speculative Data-Driven Multi-Threading. HPCA-7, Jan. 2001.
-
(2001)
HPCA-7
-
-
Rom, A.1
Sohi, G.2
-
19
-
-
0030652674
-
Dynamic instruction reuse
-
June
-
A. Sodani and G. Sohi. Dynamic Instruction Reuse. ISCA-24, June 1997.
-
(1997)
ISCA-24
-
-
Sodani, A.1
Sohi, G.2
-
21
-
-
84949037105
-
Improving value communication for thread-level speculation
-
Jan.
-
J. Steflan, et al. Improving Value Communication for Thread-Level Speculation. HPCA-6, Jan. 2000.
-
(2000)
HPCA-6
-
-
Steflan, J.1
-
22
-
-
0034441012
-
Slipstream processors: Improving both performance and fault tolerance
-
Nov.
-
K. Sundaramoorthy, Z. Purser, and E. Rotenberg. Slipstream Processors: Improving both Performance and Fault Tolerance. ASPLOS-9, Nov. 2000.
-
(2000)
ASPLOS-9
-
-
Sundaramoorthy, K.1
Purser, Z.2
Rotenberg, E.3
-
23
-
-
0029727822
-
The superthreaded architecture: Thread pipelining with run-time data dependence checking and control speculation
-
Oct
-
J.-Y. Tsai and P.-C. Yew. The Superthreaded Architecture: Thread Pipelining with Run-Time Data Dependence Checking and Control Speculation. PACT, Oct 1996.
-
(1996)
PACT
-
-
Tsai, J.-Y.1
Yew, P.-C.2
-
25
-
-
0034856097
-
Execution-based prediction using speculative slices
-
July
-
C. Zilles and G. Sohi. Execution-based Prediction Using Speculative Slices. ISCA-28, July 2001.
-
(2001)
ISCA-28
-
-
Zilles, C.1
Sohi, G.2
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