"Flea-flicker" Multipass pipelining: An alternative to the high-power out-of-order offense

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2005, Pages 319-330

  Barnes, Ronald D ^a   Ryoo, Shane ^b   Hwu, Wen Mei W ^b  

^a Krasnow Institute for Advanced Study   (United States)

^b United States of America   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPILE-TIME SCHEDULING; MICROARCHITECTURAL MODEL; MICROARCHITECTURES; MULTIPASS PIPELINING;

COMPUTATIONAL COMPLEXITY; COMPUTATIONAL METHODS; COMPUTER SIMULATION; MATHEMATICAL MODELS; MICROCOMPUTERS; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS; SCHEDULING;

PIPELINE PROCESSING SYSTEMS;

EID: 33644900150     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2005.1     Document Type: Conference Paper

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