Out-of-order commit processors

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn 10, Issue , 2004, Pages 48-59

  Cristal, Adrian ^a   Ortega, Daniel ^b   Llosa, Josep ^a   Valero, Mateo ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

IN-FLIGHT INSTRUCTIONS; MEMORY LATENCY; REORDER BUFFER (ROF);

BUFFER STORAGE; COMPUTER ARCHITECTURE; COSTS; OPTIMIZATION; PERFORMANCE; RESOURCE ALLOCATION; SHIFT REGISTERS;

MICROPROCESSOR CHIPS;

EID: 2342619439     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (32)

1. A. V. Aho, R. Sethi, and J. D. Ullman. Compilers: Principles, Techniques, and Tools. Addison-Wesley, Reading, Mass., 1986.
2. H. Akkary and M. Driscoll. A dynamic multithreading processor. In Proceedings of the 31st Annual International Symposium on Microarchitecture, pages 226-236, Dallas, Texas, Nov. 1998.
3. H. Akkary, R. Rajwar, and S. T. Srinivasan. Checkpoint processing and recovery: Towards scalable large instruction window processors. In Proceedings of the 36nd annual ACM/IEEE international symposium on Microarchitecture. IEEE Computer Society, Dec. 2003.
4. C. Asato, R. Montoye, J. Gmuender, E. Simmons, A. Ike, and J. Zasio. A 14 port 3.8ns 116 64b read-renaming register file. In 1995 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 1995.
5. A.-H. Badawy, A. Aggarwal, D. Yeung, and C.-W. Tseng. Evaluating the impact of memory system performance on software prefetching and locality optimizations. In Proceedings of the 15th International Conference on Supercomputing, pages 486-500. ACM Press, June 2001.
6. R. Balasubramonian, S. Dwarkadas, and D. Albonesi. Dynamically allocating processor resources between nearby and distant ilp. In Proceedings of the 28th Annual International Symposium on on Computer Architecture, pages 26-37. ACM Press, July 2001.
7. E. Brekelbaum, J. Rupley, C. Wilkerson, and B. Black. Hierarchical scheduling windows. In Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture, pages 27-36. IEEE Computer Society Press, Nov. 2002.
8. A. Cristal, J. Martínez, J. Llosa, and M. Valero. A case for resource-conscious out-of-order processors. In Computer Architecture Letters, volume 2, Oct. 2003. MEDEA - Memory Performance: Dealing with Applications, Systems and Architecture, Sept. 2003. Technical Report UPC-DAC-2003-45, July 2003.
9. A. Cristal, J. Martínez, J. Llosa, and M. Valero. Ephemeral registers with multicheckpointing. Technical Report UPC-DAC-2003-51, UPC, Oct. 2003.
10. A. Cristal, D. Ortega, J. Llosa, and M. Valero. Kilo-instruction processors (invited paper). In Proceedings of 5th International Symposium of High Performance Computing - LNCS 2858, pages 10-25. Springer, Oct. 2003.
11. A. Cristal, M. Valero, A. Gonzalez, and J. Llosa. Large virtual robs by processor checkpointing. Technical Report UPC-DAC-2002-39 (Submitted to Micro 35), Universidad Politécnica de Cataluña, Department of Computer Architecture, July 2002.
12. C. Gniady, B. Falsafi, and T. N. Vijaykumar. Is SC + ILP = RC? In Proceedings of the 26th Annual International Symposium on Computer Architecture, pages 162-171, Atlanta, Georgia, May 1999. IEEE Computer Society TCCA and ACM SIGARCH. Computer Architecture News, 27(2), May 1999.
13. J. Hennessy and D. Patterson. Computer Architecture. A Quantitative Approach. Second Edition. Morgan Kaufmann Publishers, San Francisco, 1996.
14. W. Hwu and Y. N. Patt. Checkpoint repair for out-of-order execution machines. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 18-26. ACM Press, June 1987.
15. N. P. Jouppi and P. Ranganathan. The relative importance of memory latency, bandwidth, and branch limits to performance. In Workshop of Mixing Logic and DRAM: Chips that Compute and Remember. ACM Press, 1997.
16. T. Karkhanis and J. E. Smith. A day in the life of a data cache miss. In Workshop on Memory Performance Issues, in conjunction with ISCA, May 2002.
17. J. Keller. The 21264: A superscalar Alpha processor with out-of-order execution. In 9th Annual Microprocessor Forum, San Jose, California, Oct. 1996.
18. A. Lebeck, J. Koppanalil, T. Li, J. Patwardhan, and E. Rotenberg. A large, fast instruction window for tolerating cache misses. In Proceedings of the 29th Annual International Symposium on Computer Architecture, pages 59-70. IEEE Computer Society, May 2002.
19. J. Martinez, A. Cristal, M. Valero, and J. Llosa. Ephemeral registers. Technical Report CSL-TR-2003-1035, Cornell Computer Systems Lab, June 2003.
20. J. Martínez, J. Renau, M. Huang, M. Prvulovic, and J. Torrellas. Cherry: checkpointed early resource recycling in out-of-order microprocessors. In Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture, pages 3-14. IEEE Computer Society Press, Nov. 2002.
21. T. Monreal, A. González, M. Valero, J. González, and V. Viñals. Delaying physical register allocation through virtual-physical registers. In Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, pages 186-192. IEEE Computer Society, Nov. 1999.
22. M. Moudgill, K. Pingali, and S. Vassiliadis. Register renaming and dynamic speculation: an alternative approach. In Proceedings of the 26th Annual International Symposium on Microarchitecture, pages 202-213. IEEE Computer Society Press, Dec. 1993.
23. O. Mutlu, J. Stark, C. Wilkerson, and Y. Patt. Runahead execution: An alternative to very large instruction windows for out-of-order processors. In Proceedings of the 9th International Symposium on High-Performance Computer Architecture, Anaheim, California, Feb. 2003.
24. S. Palacharla, N. Jouppi, and J. Smith. Complexity-effective superscalar processors. In Proceedings of the 24th International Symposium on Computer Architecture, pages 206-218. ACM Press, June 1997.
25. D. Pressel. Fundamental limitations on the use of prefetching and stream buffers for scientific applications. In Proceedings of the 2001 ACM Symposium on Applied computing, pages 554-559. ACM Press, Mar. 2001.
26. P. Ranganathan, V. Pai, and S. Adve. Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency models. In Proceedings of the 9th Annual ACM Symposium on Parallel Algorithms and Architectures, pages 199-210. ACM Press, June 1997.
27. E. Rotenberg, Q. Jacobson, Y. Sazeides, and J. Smith. Trace processors. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 138-148, Research Triangle Park, North Carolina, Dec. 1997.
28. T. Sherwood, E. Perelman, and B. Calder. Basic block distribution analysis to find periodic behavior and simulation points in applications. In Proceedings of the Intl. Conference on Parallel Architectures and Compilation Techniques, pages 3-14, Sept. 2001.
29. K. Skadron, P. Ahuja, M. Martonosi, and D. Clark. Branch prediction, instruction-window size, and cache size: Performance trade-offs and simulation techniques. In IEEE Transactions on Computers, volume 48, pages 1260-1281. IEEE Computer Society, Nov. 1999.
30. J. E. Smith and A. R. Pleszkun. Implementing precise interrupts in pipelined processors. In IEEE Transactions on Computers, volume 37, pages 562-573. IEEE Computer Society, May 1988.
31. G. Sohi, S. Breach, and T. N. Vijaykumar. Multiscalar processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 414-425, Santa Margherita Ligure, Italy, June 1995. ACM SIGARCH and IEEE Computer Society TCCA. Computer Architecture News, 23(2), May 1994.
32. S. Srinivasan and A. Lebeck. Load latency tolerance in dynamically scheduled processors. In Proceedings of the 31st Annual International Symposium on Microarchitecture, pages 148-159, Dallas, Texas, Nov. 1998.