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Volumn 31, Issue , 2004, Pages 90-101

Memory ordering: A value-based approach

Author keywords

[No Author keywords available]

Indexed keywords

FIFO; INSTRCUTIONS-PER-CYCLE (IPC); LSQ; VALUE-BASED DESIGN;

EID: 4644289583     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (52)

References (26)
  • 3
    • 0033321638 scopus 로고    scopus 로고
    • DIVA: A reliable substrate for deep submicron microarchitecture design
    • Haifa, Israel, November
    • T. Austin. "DIVA: A reliable substrate for deep submicron microarchitecture design." In Proc. of the 32nd Intl. Symp. on Microarchitecture, pages 196-207, Haifa, Israel, November 1999.
    • (1999) Proc. of the 32nd Intl. Symp. on Microarchitecture , pp. 196-207
    • Austin, T.1
  • 12
    • 85008031236 scopus 로고    scopus 로고
    • Minnespec: A new SPEC benchmark workload for simulation-based computer architecture research
    • June
    • A. KleinOsowski and D. J. Lilja. "Minnespec: A new SPEC benchmark workload for simulation-based computer architecture research." Computer Architecure Letters, 1, June 2002.
    • (2002) Computer Architecure Letters , vol.1
    • Kleinosowski, A.1    Lilja, D.J.2
  • 17
    • 0033357302 scopus 로고    scopus 로고
    • Dynamic memory disambiguation in the presence of out-of-order store issuing
    • November
    • S. Onder and R. Gupta. "Dynamic memory disambiguation in the presence of out-of-order store issuing." In Proc. of the 32nd Intl. Symp. on Microarchitecture, November 1999.
    • (1999) Proc. of the 32nd Intl. Symp. on Microarchitecture
    • Onder, S.1    Gupta, R.2
  • 19
    • 0035691607 scopus 로고    scopus 로고
    • Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources
    • December
    • D. Ponomarev, G. Kucuk, and K. Ghose. "Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources." In Proc. of the 34th Intl. Symp. on Microarchitecture, December 2001.
    • (2001) Proc. of the 34th Intl. Symp. on Microarchitecture
    • Ponomarev, D.1    Kucuk, G.2    Ghose, K.3
  • 22
    • 2342635671 scopus 로고    scopus 로고
    • Cacti 3.0: An integrated cache timing, power, and area model
    • Compaq Western Research Lab Research Report
    • P. Shivakumar and N. P. Jouppi. "Cacti 3.0: An integrated cache timing, power, and area model." Technical Report 2001/2, Compaq Western Research Lab Research Report, 2001.
    • (2001) Technical Report , vol.2001 , Issue.2
    • Shivakumar, P.1    Jouppi, N.P.2
  • 25
    • 0030129806 scopus 로고    scopus 로고
    • The MIPS R10000 superscalar microprocessor
    • April
    • K. C. Yeager. "The MIPS R10000 superscalar microprocessor." IEEE Micro, 16(2):28-40, April 1996.
    • (1996) IEEE Micro , vol.16 , Issue.2 , pp. 28-40
    • Yeager, K.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.