Address-value delta (AVD) prediction: Increasing the effectiveness of runahead execution by exploiting regular memory allocation patterns

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2005, Pages 233-244

  Mutlu, Onur ^a   Kim, Hyesoon ^a   Patt, Yale N ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDRESS-VALUE DELTA (AVD) PREDICTION; EXECUTION TIME; LONG-LATENCY CACHE MISSES; MEMORY ALLOCATION PATTERNS;

CACHE MEMORY; DATA STRUCTURES; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS;

STORAGE ALLOCATION (COMPUTER);

EID: 33644917917     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2005.11     Document Type: Conference Paper

References (31)

1. M. Bekerman, S. Jourdan, R. Ronen, G. Kirshenboim, L. Rappoport, A. Yoaz, and U. Weiser. Correlated load-address predictors. In ISCA-26, 1999.
2. L. Ceze, K. Strauss, J. Tuck, J. Renau, and J. Torrellas. CAVA: Hiding L2 misses with checkpoint-assisted value prediction. Computer Architecture Letters, 3, Dec. 2004.
3. Y. Chou, B. Fahs, and S. Abraham. Microarchitecture optimizations for exploiting memory-level parallelism. In ISCA-31, 2004.
4. J. D. Collins, S. S air, B. Calder, and D. M. Tullsen. Pointer cache assisted prefetching. In MICRO-35, 2002.
5. R. Cooksey, S. Jourdan, and D. Grunwald. A stateless, content-directed data prefetching mechanism. In ASPLOS-X, 2002.
6. J. Dundas and T. Mudge. Improving data cache performance by pre-executing instructions under a cache miss. In ICS-1997, 1997.
7. R. J. Eickemeyer and S. Vassiliadis. A load-instruction unit for pipelined processors. IBM Journal of Research and Development, 37:547-564, 1993.
8. A. Glew. MLP yes! ILP no! In ASPLOS Wild and Crazy Idea Session '98, Oct. 1998.
9. M. K. Gowan, L. L. Biro, and D. B. Jackson. Power considerations in the design of the Alpha 21264 microprocessor. In DAC-35, 1998.
10. D. Joseph and D. Grunwald. Prefetching using Markov predictors. In ISCA-24, 1997.
11. M. Karlsson, R Dahlgren, and P. Strenstrom. A prefetching technique for irregular accesses to linked data structures. In HPCA-6, 2000.
12. N. Kirman, M. Kirman, M. Chaudhuri, and J. F. Martínez. Checkpointed early load retirement. In HPCA-11, 2005.
13. A. KleinOsowski and D. J. Lilja. MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research. Computer Architecture Letters, 1, June 2002.
14. M. H. Lipasti, W. J. Schmidt, S. R. Kunkel, and R. R. Roediger. SPAID: Software prefetching in pointer- and call-intensive environments. In MICRO-28, 1995.
15. M. H. Lipasti, C. Wilkerson, and J. P. Shen. Value locality and load value prediction. In ASPLOS-VII, 1996.
16. C.-K. Luk and T. C. Mowry. Compiler-based prefetching for recursive data structures. In ASPLOS-VII, 1996.
17. O. Mutlu, H. Kim, and Y. N. Patt. Techniques for efficient processing in runahead execution engines. In ISCA-32, 2005.
18. O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt. Runahead execution: An alternative to very large instruction windows for out-of-order processors. In HPCA-9, 2003.
19. O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt. Runahead execution: An effective alternative to large instruction windows. IEEE Micro, 23(6):20-25, 2003.
20. P. Racunas. Reducing Load Latency Through Memory Instruction Characterization. PhD thesis, University of Michigan, 2003.
21. A. Rogers, M. C. Carlisle, J. Reppy, and L. Hendren. Supporting dynamic data structures on distributed memory machines. ACM Transactions on Programming Languages and Systems, 17(2):233-263, Mar. 1995.
22. A. Roth, A. Moshovos, and G. S. Sohi. Dependence based prefetching for linked data structures. In ASPLOS-VIII, 1998.
23. A. Roth and G. S. Sohi. Effective jump-pointer prefetching for linked data structures. In ISCA-26, 1999.
24. Y. Sazeides and J. E. Smith. The predictability of data values. In MICRO-30, 1997.
25. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In ASPLOS-X, 2002.
26. E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In ISCA-29, 2002.
27. K. Wang and M. Franklin. Highly accurate data value prediction using hybrid predictors. In MICRO-30, 1997.
28. M. V. Wilkes. The memory gap and the future of high performance memories. ACM Computer Architecture News, 29(1):27, Mar. 2001.
29. W. Wulf and S. McKee. Hitting the memory wall: Implications of the obvious. ACM Computer Architecture News, 23(1):20-24, Mar. 1995.
30. C.-L. Yang and A. R. Lebeck. Push vs. pull: Data movement for linked data structures. In ICS-2000, 2000.
31. H. Zhou and T. M. Conte. Enhancing memory level parallelism via recovery-free value prediction. In ICS-17, 2003.