Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 8, 2007, Pages 869-879

  Murali, Srinivasan ^a,b   Atienza, David ^a,c,d   Meloni, Paolo ^e   Carta, Salvatore ^e   Benini, Luca ^a,f   De Micheli, Giovanni ^a,c   Raffo, Luigi ^e  

^a IEEE   (United States)

^b STANFORD UNIVERSITY   (United States)

^c EPFL   (Switzerland)

^d UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^e UNIVERSITY OF CAGLIARI   (Italy)

^f UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Bandwidth; Chip multiprocessors (CMPs); Networks on chip (NoCs); Power consumption; Predictability; Synthesis; Throughput

Indexed keywords

BANDWIDTH; ELECTRIC POWER UTILIZATION; INTERCONNECTION NETWORKS; THROUGHPUT;

CHIP MULTIPROCESSORS (CMP); INTERCONNECT ARCHITECTURES; NETWORKS-ON-CHIP (NOC); PREDICTABILITY;

MICROPROCESSOR CHIPS;

EID: 34547397357     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.900742     Document Type: Article

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