메뉴 건너뛰기




Volumn , Issue , 2006, Pages 389-400

High-level power analysis for multi-core chips

Author keywords

Chip multiprocessor (CMP); Multi core; Power analysis; Simulation; System on a chip (SoC)

Indexed keywords

POWER ANALYSIS; PROCESSOR CORES; SYSTEM-ON-A-CHIP (SOC);

EID: 34547205571     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1176760.1176807     Document Type: Conference Paper
Times cited : (23)

References (42)
  • 2
    • 0034785285 scopus 로고    scopus 로고
    • L. Benini and G. De Micheli. Powering Networks on Chip. In Proc. of the International Symposium on System Synthesis, pp. 33-38, Oct. 2001.
    • L. Benini and G. De Micheli. Powering Networks on Chip. In Proc. of the International Symposium on System Synthesis, pp. 33-38, Oct. 2001.
  • 3
    • 0033719421 scopus 로고    scopus 로고
    • D. Brooks et al. Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In Proc. of the International Symposium on Computer Architecture, pp. 83-94, June 2000.
    • D. Brooks et al. Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In Proc. of the International Symposium on Computer Architecture, pp. 83-94, June 2000.
  • 4
    • 21644483075 scopus 로고    scopus 로고
    • M. Burtscher and I. Ganusov. Automatic Synthesis of High-Speed Processor Simulators. In Proc. of the International Symposium on Microarchitecture, pp. 55-66, Dec. 2004.
    • M. Burtscher and I. Ganusov. Automatic Synthesis of High-Speed Processor Simulators. In Proc. of the International Symposium on Microarchitecture, pp. 55-66, Dec. 2004.
  • 5
    • 33745215854 scopus 로고    scopus 로고
    • G. Chen et al. Compiler-Directed Channel Allocation for Saving Power in on-Chip Networks. In Proc. of the Symposium on Principles of Programming Languages, pp. 194-205, Jan. 2006.
    • G. Chen et al. Compiler-Directed Channel Allocation for Saving Power in on-Chip Networks. In Proc. of the Symposium on Principles of Programming Languages, pp. 194-205, Jan. 2006.
  • 6
    • 33746085616 scopus 로고    scopus 로고
    • G. Chen et al. Reducing NoC Energy Consumption Through Compiler-Directed Channel Voltage Scaling. In Proc. of the Conference on Programming Language Design and Implementation, pp. 193-203, June 2006.
    • G. Chen et al. Reducing NoC Energy Consumption Through Compiler-Directed Channel Voltage Scaling. In Proc. of the Conference on Programming Language Design and Implementation, pp. 193-203, June 2006.
  • 7
    • 34547163294 scopus 로고    scopus 로고
    • J. W. Chen et al. SimWattch: An Approach to Integrate Complete-System with User-Level Performance/Power Simulators. In Proc. of the International Symposium on Performance Analysis of Systems and Software, pp. 1-10, March 2003.
    • J. W. Chen et al. SimWattch: An Approach to Integrate Complete-System with User-Level Performance/Power Simulators. In Proc. of the International Symposium on Performance Analysis of Systems and Software, pp. 1-10, March 2003.
  • 8
    • 0034848112 scopus 로고    scopus 로고
    • W. J. Dally and B. Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. In Proc. of the Design Automation Conference, pp. 684-689, June 2001.
    • W. J. Dally and B. Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. In Proc. of the Design Automation Conference, pp. 684-689, June 2001.
  • 9
    • 0242577987 scopus 로고    scopus 로고
    • Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox
    • Sept.-Oct
    • L. Eeckhout et al. Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox. IEEE Micro, Vol. 23, No. 5, pp. 26-38, Sept.-Oct. 2003.
    • (2003) IEEE Micro , vol.23 , Issue.5 , pp. 26-38
    • Eeckhout, L.1
  • 10
    • 27944434356 scopus 로고    scopus 로고
    • N. Eisley and L.-S. Peh. High-Level Power Analysis for on-Chip Networks. In Proc. of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems, pp. 104-115, Sept. 2004, LUNA: Available [online] http://www.princeton.edu/~eisley/LUNA.html.
    • N. Eisley and L.-S. Peh. High-Level Power Analysis for on-Chip Networks. In Proc. of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems, pp. 104-115, Sept. 2004, LUNA: Available [online] http://www.princeton.edu/~eisley/LUNA.html.
  • 11
    • 34547141580 scopus 로고    scopus 로고
    • Gigascale Systems Research Center GSRC, Available [online
    • Gigascale Systems Research Center (GSRC), 2006. Available [online] http://www.gigascale.org/roadmap/.
    • (2006)
  • 12
    • 0030652733 scopus 로고    scopus 로고
    • C-T. Hsieh et al. Profile-Driven Program Synthesis for Evaluation of System Power Dissipation. In Proc. of the Design Automation Conference, pp. 576-581, June 1997.
    • C-T. Hsieh et al. Profile-Driven Program Synthesis for Evaluation of System Power Dissipation. In Proc. of the Design Automation Conference, pp. 576-581, June 1997.
  • 13
    • 33748856569 scopus 로고    scopus 로고
    • C. Isci and M. Martonosi. Phase Characterization for Power: Evaluating Control-Flow-Based and Event-Counter-Based Techniques. In Proc. of the International Symposium on High Performance Computer Architecture, pp. 121-132, Feb. 2006.
    • C. Isci and M. Martonosi. Phase Characterization for Power: Evaluating Control-Flow-Based and Event-Counter-Based Techniques. In Proc. of the International Symposium on High Performance Computer Architecture, pp. 121-132, Feb. 2006.
  • 14
    • 85087534725 scopus 로고    scopus 로고
    • J. S. Kim et al. Energy Characterization of a Tiled Architecture Processor with on-Chip Networks. In Proc. of the International Symposium on Low Power Electronics and Design, pp. 424-427, Aug. 2003.
    • J. S. Kim et al. Energy Characterization of a Tiled Architecture Processor with on-Chip Networks. In Proc. of the International Symposium on Low Power Electronics and Design, pp. 424-427, Aug. 2003.
  • 15
    • 20344374162 scopus 로고    scopus 로고
    • Niagara: A 32-Way Multithreaded Sparc Processor
    • March/April
    • P. Kongetira et al. Niagara: A 32-Way Multithreaded Sparc Processor. IEEE Micro, Vol. 25, No. 2, pp. 21-29, March/April 2005.
    • (2005) IEEE Micro , vol.25 , Issue.2 , pp. 21-29
    • Kongetira, P.1
  • 17
    • 0022583632 scopus 로고    scopus 로고
    • S. McFarling and J. Hennessy. Reducing the Cost of Branches. In Proc. of the International Symposium on Computer Architecture, pp. 396-403, June, 1986.
    • S. McFarling and J. Hennessy. Reducing the Cost of Branches. In Proc. of the International Symposium on Computer Architecture, pp. 396-403, June, 1986.
  • 18
    • 21044452345 scopus 로고    scopus 로고
    • Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors
    • June
    • B. H. Meyer at. al. Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors. IEEE Transactions on Computers, Vol. 54, No. 6, June 2005.
    • (2005) IEEE Transactions on Computers , vol.54 , Issue.6
    • Meyer, B.H.1    at. al2
  • 19
    • 34547228085 scopus 로고    scopus 로고
    • MIT Raw Team, personal communication, 2006.
    • MIT Raw Team, personal communication, 2006.
  • 20
    • 4644316767 scopus 로고    scopus 로고
    • Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor
    • June
    • J. Oliver et al. Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. In Proc. of the International Symposium on Computer Architecture, pp. 150-161, June 2004.
    • (2004) Proc. of the International Symposium on Computer Architecture , pp. 150-161
    • Oliver, J.1
  • 21
    • 34547140622 scopus 로고    scopus 로고
    • V. S. Pai et al. RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors. In Proc. of the International Symposium on High Performance Computer Architecture, pp. 72-83, Feb. 1997.
    • V. S. Pai et al. RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors. In Proc. of the International Symposium on High Performance Computer Architecture, pp. 72-83, Feb. 1997.
  • 22
    • 85165530188 scopus 로고    scopus 로고
    • M. Pedram and Q. Wu. Design Considerations for Battery-Powered Electronics. In Proc. of the Design Automation Conference, pp. 861-866, June 1999.
    • M. Pedram and Q. Wu. Design Considerations for Battery-Powered Electronics. In Proc. of the Design Automation Conference, pp. 861-866, June 1999.
  • 23
  • 24
    • 27344435504 scopus 로고    scopus 로고
    • D. Pham et al. The Design and Implementation of a First-Generation Cell Processor. In Proc. of the International Solid-State Circuits Conference, pp. 184-185, March 2005.
    • D. Pham et al. The Design and Implementation of a First-Generation Cell Processor. In Proc. of the International Solid-State Circuits Conference, pp. 184-185, March 2005.
  • 25
    • 34547144622 scopus 로고    scopus 로고
    • Available [online
    • PoPNet Simulator, 2006. Available [online] http://www.princeton.edu/ ~lshang/popnet.html.
    • (2006) PoPNet Simulator
  • 26
    • 0037669851 scopus 로고    scopus 로고
    • K. Sankaralingam et al. Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. In Proc. of the International Symposium on Computer Architecture, pp. 422-433, June 2003.
    • K. Sankaralingam et al. Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. In Proc. of the International Symposium on Computer Architecture, pp. 422-433, June 2003.
  • 27
    • 8344233355 scopus 로고    scopus 로고
    • R. Sasanka et al. The Energy Efficiency of CMP vs. SMT for Multimedia Workloads. In Proc. of the International Conference on Supercomputing, pp. 196-206, June 2004.
    • R. Sasanka et al. The Energy Efficiency of CMP vs. SMT for Multimedia Workloads. In Proc. of the International Conference on Supercomputing, pp. 196-206, June 2004.
  • 28
    • 1142305187 scopus 로고    scopus 로고
    • L. Shang et al. PowerHerd: Dynamically Satisfying Peak Power Constraints in Interconnection Networks. In Proc. of the International Conference on Supercomputing, pp. 98-108, June 2003.
    • L. Shang et al. PowerHerd: Dynamically Satisfying Peak Power Constraints in Interconnection Networks. In Proc. of the International Conference on Supercomputing, pp. 98-108, June 2003.
  • 29
    • 21644444692 scopus 로고    scopus 로고
    • L. Shang et al. Thermal Modeling, Characterization, and Management of On-Chip Networks. In Proc. of the International Symposium on Microarchitecture, pp. 67-78, Dec. 2004.
    • L. Shang et al. Thermal Modeling, Characterization, and Management of On-Chip Networks. In Proc. of the International Symposium on Microarchitecture, pp. 67-78, Dec. 2004.
  • 30
    • 0036953769 scopus 로고    scopus 로고
    • Automatically Characterizing Large Scale Program Behavior
    • Oct
    • T. Sherwoood et al. Automatically Characterizing Large Scale Program Behavior. ACM SIGPLAN Notices, Vol. 37, No. 10, pp. 45-57, Oct. 2002.
    • (2002) ACM SIGPLAN Notices , vol.37 , Issue.10 , pp. 45-57
    • Sherwoood, T.1
  • 31
    • 34547154596 scopus 로고    scopus 로고
    • Available [online
    • Simics, 2006. Available [online]: www.simics.net.
    • (2006)
    • Simics1
  • 32
    • 34547179740 scopus 로고    scopus 로고
    • Available [online
    • SimpleScalar LLC, 2006. Available [online]: http://www.simplescalar.com.
    • (2006)
    • SimpleScalar, L.L.C.1
  • 33
    • 29144475874 scopus 로고    scopus 로고
    • V. Soteriou et al. Software-Directed Power-Aware Interconnection Networks. In Proc. of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 274-285, Sept. 2005.
    • V. Soteriou et al. Software-Directed Power-Aware Interconnection Networks. In Proc. of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 274-285, Sept. 2005.
  • 34
    • 4644353790 scopus 로고    scopus 로고
    • M. B. Taylor et al. Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. In Proc. of the International Symposium on Computer Architecture, pp. 2-13, June 2004.
    • M. B. Taylor et al. Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. In Proc. of the International Symposium on Computer Architecture, pp. 2-13, June 2004.
  • 36
    • 34547206494 scopus 로고    scopus 로고
    • The Standard Performance Evaluation Corporation, Available [online
    • The Standard Performance Evaluation Corporation, 2006. Available [online]: http://www.spec.org.
    • (2006)
  • 38
    • 0028711545 scopus 로고    scopus 로고
    • Vivek Tiwari et al. Power Analysis of Embedded Software: A First Step towards Software Power Minimization. In Proc. of the 1994 International Conference on Computer-Aided Design, pp. 384-390, Aug. 1994.
    • Vivek Tiwari et al. Power Analysis of Embedded Software: A First Step towards Software Power Minimization. In Proc. of the 1994 International Conference on Computer-Aided Design, pp. 384-390, Aug. 1994.
  • 39
    • 84983179859 scopus 로고    scopus 로고
    • M. Vachharajani et al. Microarchitectural Exploration with Liberty. In Proc. of the International Symposium on Microarchitecture, pp. 271-282, Nov. 2002.
    • M. Vachharajani et al. Microarchitectural Exploration with Liberty. In Proc. of the International Symposium on Microarchitecture, pp. 271-282, Nov. 2002.
  • 40
    • 84948976085 scopus 로고    scopus 로고
    • H. Wang et al. Orion: A Power-Performance Simulator for Interconnection Networks. In Proc. of the International Symposium on Microarchitecture, pp. 294-305, Nov. 2002.
    • H. Wang et al. Orion: A Power-Performance Simulator for Interconnection Networks. In Proc. of the International Symposium on Microarchitecture, pp. 294-305, Nov. 2002.
  • 41
    • 0033712191 scopus 로고    scopus 로고
    • W. Ye et al. The Design and Use of SimplePower: A Cycle Accurate Energy Estimation Tool. In Proc. of the Design Automation Conference, pp. 340-345, June 2000.
    • W. Ye et al. The Design and Use of SimplePower: A Cycle Accurate Energy Estimation Tool. In Proc. of the Design Automation Conference, pp. 340-345, June 2000.
  • 42
    • 0030129806 scopus 로고    scopus 로고
    • The MIPS R10000 Superscalar Microprocessor
    • April
    • K. C. Yeager. The MIPS R10000 Superscalar Microprocessor. IEEE Micro, Vol. 16, No. 2, pp. 28-40, April 1996.
    • (1996) IEEE Micro , vol.16 , Issue.2 , pp. 28-40
    • Yeager, K.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.