Software-directed power-aware interconnection networks

CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Volumn , Issue , 2005, Pages 274-285

  Soteriou, Vassos ^a   Eisley, Noel ^a   Peh, Li Shiuan ^a  

^a Princeton University   (United States)

Author keywords

Communication links; Dynamic voltage scaling; Interconnection networks; Networks on a chip (NoC); Simulation.; Software directed power reduction

Indexed keywords

BENCHMARKING; COMPUTER ARCHITECTURE; COMPUTER NETWORKS; COMPUTER SOFTWARE; ELECTRIC POWER UTILIZATION; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; TELECOMMUNICATION LINKS;

DYNAMIC VOLTAGE SCALING; SOFTWARE-DIRECTED POWER REDUCTION;

INTERCONNECTION NETWORKS;

EID: 29144475874     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1086297.1086333     Document Type: Conference Paper

References (34)

1. T. D. Burd and R. W. Brodersen. Design issues for dynamic voltage scaling. In Proc. of the 5th International Symposium on Low Power Electronics and Design (ISLPED'00), pp. 9-14, 2000.
2. X. Chen and L.-S. Peh. Exploring the design space of power-aware opto-electronic network systems. In Proc. of the 11th International Symposium on High-Performance Computer Architecture (HPCA-11), pp. 120-131, Feb. 2005.
3. W. J. Dally and B. Towles. Route packets, not wires: On-chip interconnection networks, In Proc. of the of 41st Design Automation Conference (DAC-41), pp. 684-689, June 2001.
4. J. Duato. A theory of fault-tolerant routing in wormhole networks. IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 8, No. 8, Aug. 1997.
5. N. Eisley and L.-S. Peh. High-level analysis for on-chip networks. In Proc. of the 7th International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES'04), pp. 104-115, Sept. 2004. (LUNA, [online] http://www.princeton.edu/~eisley/LUNA.html)
6. J. Hu and R. Marculescu. Energy-aware communication and task scheduling for network-on-chip architectures under real-time Constraints. In Proc. of Design, Automation and Test in Europe Conference and Exhibition (DATE'04), pp. 10234-10239, Feb. 2004.
7. InfiniBand Trade Alliance, The InfiniBand architecture, [online] http://www.infinibandta.org.
8. A. Jalabert et. al. pipesCompiler: A tool for instantiating application specific networks on chip. In Proc. of Design, Automation and Test in Europe Conference and Exhibition (DATE'04), pp. 20884-20889, Feb. 2004.
9. I. Kadayif et. al. Exploiting processor workload heterogeneity for reducing energy consumption in chip multiprocessors. In Proc. of the Design, Automation and Test in Europe Conference and Exhibition (DATE'04), pp. 21158-21163 Feb. 2004.
10. E. J. Kim et. al. Energy optimization techniques in cluster interconnects. In Proc. of the International Symposium on Low Power Electronics and Design (ISLPED'03), pp. 459-464, Aug. 2003.
11. J. Kim and M. Horowitz. Adaptive supply serial links with sub-IV operation and per-pin clock recovery. In Proc. International Solid-State Circuits Conference (ISSCC), pp. 1403-1413, Feb. 2002.
12. J. S. Kim et. al. Energy characterization of a tiled architecture processor with on-chip networks. In Proc. of the 8th International Symposium on Low Power Electronics and Design (ISLPED'03), pp. 424-427, Aug. 2003.
13. L. Kleinrock. Queueing Systems, Vol. 1. John Wiley and Sons. New York, NY, 1975.
14. C. Lee et. al. Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In Proc. of the 30th International Symposium on Microarchitecture (MICRO-30), pp. 330-335, Nov. 1997.
15. W. Lee et. al. Space-time scheduling of instruction-level parallelism on a Raw machine. In Proc. of the 8th International Conference on Architectural Support for Programming Language and Operating Systems (ASPLOS-8), pp. 46-57, Oct. 1998.
16. J. Luo et. al. Simultaneous dynamic voltage scaling of processors and communication links in real-time distributed embedded systems. In Proc. of Design, Automation and Test in Europe Conference and Exhibition (DATE'03), pp. 11150-11151, 2003.
17. S. S. Mukherjee et, al. The Alpha 21364 network architecture. IEEE Micro, 22(1), 2002.
18. V. S. Pai et. al. RSIM: An execution-driven simulator for ILP-based shared-memory multiprocessors and uniprocessors. In IEEE Technical Committee on Computer Architecture Newsletter (TCCA), 35(11), pp. 37-48, Oct. 1997.
19. C. Patel et. al. Power-constrained design of multiprocessor interconnection networks. In Proc. of the 15th International Conference on Computer Design (ICCD'97), pp. 408-416, Oct. 1997.
20. PoPNet. (online] http://www.princeton.edu/edu/~lshang/popnet.html
21. K. Sankaralingam et. al. Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture. In Proc. of the 30th International Symposium on Computer Architecture (ISCA-30), pp. 422-422, June 2003.
22. H. Saputra et. al. Energy-conscious compilation based on voltage scaling. In Proc. of the Joint Conference on Languages, Compilers and Tools for Embedded Systems: Software and Compilers for Embedded Systems, pp. 2-11, June 2002.
23. Semiconductor Industry Association. International Technology Roadmap for Semiconductors, 2001: [online] http://public.itrs.net/Files/2001ITRS/Home.htm
24. L. Shang et. al. Dynamic voltage scaling with links for power optimization of interconnection networks. In Proc. of the 9th International Symposium on High-Performance Computer Architecture (HPCA-9), pp. 79-90, Feb. 2003.
25. V. Soteriou and L.-S. Peh. Design-space exploration of power-aware on/off interconnection networks. In Proc. of the 22nd International Conference on Computer Design (ICCD'04), pp. 510-517, Oct. 2004.
26. J. M. Stine and N. P. Carter. Comparing adaptive routing and dynamic voltage scaling for link power reduction. Computer Architecture Letters, Vol. 3, June 2004.
27. M. B. Taylor et. al. Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams. In Proc. of the 31st International Symposium on Computer Architecture (ISCA-31), pp. 2-13, June 2004.
28. The Standard Performance Evaluation Corporation. [online]http://www.spec. org/
29. H. Wang et al. Orion: A power-performance simulator for interconnection networks. In Proc. of the 35th International Symposium on Microarchitecture (MICRO-35), pp. 294-305, Nov. 2002.
30. G. Wei et. al. A variable-frequency parallel I/O interface with adaptive power-supply regulation. Journal of Solid-State Circuits, 35(11):16001610, Nov. 2000.
31. R. Wilson et. al. SUIF: An infrastructure for research on parallelizing and optimizing compilers. ACM SIGPLAN Notices, 29(12), Dec. 1996.
32. S. C. Woo et. al. The SPLASH-2 programs: characterization and methodological considerations. In Proc. of the 22nd International Symposium on Computer Architecture (ISCA-22), pp. 24-36, June 1995.
33. F. Worm et. al. An adaptive low-power transmission scheme for on-chip networks. In Proc. of the International Symposium on System Synthesis (ISSS), pp. 92-100, 2002.
34. F. Xie et. al. Compile-time dynamic voltage scaling settings: opportunities and limits. In Proc. of Programming Language Design and Implementation (PLDI), pp. 49-62, June 2003.