Synchroscalar: A multiple clock domain, power-aware, tile-based embedded processor

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn 31, Issue , 2004, Pages 150-161

  Oliver, John ^a   Rao, Ravishankar ^a   Sultana, Paul ^a   Crandall, Jedidiah ^a   Czernikowski, Erik ^a   Jones IV, Leslie W ^b   Franklin, Diana ^b   Akella, Venkatesh ^a   Chong, Frederic T ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b CALIFORNIA POLYTECHNIC STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSORS (DSP); EMBEDDED APPLICATIONS; SYNCHROSCALAR; VOLTAGE SCALING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; BENCHMARKING; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; IMAGE PROCESSING; NETWORK PROTOCOLS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; SIGNAL PROCESSING;

PROGRAM PROCESSORS;

EID: 4644316767     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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