Power-performance simulation and design strategies for single-chip heterogeneous multiprocessors

IEEE Transactions on Computers

Volumn 54, Issue 6, 2005, Pages 684-697

  Meyer, Brett H ^a   Pieper, Joshua J ^b   Paul, JoAnn M ^a   Nelson, Jeffrey E ^a   Pieper, Sean M ^c   Rowe, Anthony G ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b University of Wisconsin Madison ^*  (United States)

^c UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

Design aids; Energy aware systems; Integration and modeling; Low power design; Performance analysis; Power management; System architectures

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PERFORMANCE; PROGRAM COMPILERS;

ENERGY AWARE SYSTEMS; LOW POWER DESIGN; PERFORMANCE ANALYSIS; POWER MANAGEMENT; SINGLE CHIP HETEROGENEOUS MULTIPROCESSORS; SYSTEM ARCHITECTURE;

MULTIPROCESSING SYSTEMS;

EID: 21044452345     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2005.103     Document Type: Article

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