Reducing NoC energy consumption through compiler-directed channel voltage scaling

Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

Volumn 2006, Issue , 2006, Pages 193-203

  Chen, Guangyu ^a   Li, Feihui ^a   Kandemir, Mahmut ^a   Irwin, Mary Jane ^a  

^a The Pennsylvania State University   (United States)

Author keywords

Compiler; Energy; Network on Chip

Indexed keywords

BENCHMARKING; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; ELECTRIC POTENTIAL; EMBEDDED SYSTEMS; ENERGY UTILIZATION; PROGRAM COMPILERS; COMPUTER HARDWARE; ELECTRIC POWER UTILIZATION; OPTIMIZATION;

ENERGY; ENERGY SAVINGS; NETWORK-ON-CHIP; VOLTAGE/FREQUENCY SCALING; COMMUNICATION ARCHITECTURES; FREQUENCY SCALING SCHEME; NOC (NETWORK-ON-CHIP); POINT-TO-POINT COMMUNICATION CHANNELS;

MICROPROCESSOR CHIPS; SOFTWARE ARCHITECTURE;

EID: 33746085616     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1133981.1134004     Document Type: Conference Paper

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