Energy Characterization of a Tiled Architecture Processor with On-Chip Networks

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2003, Pages 424-427

  Kim, Jason Sungtae ^a   Taylor, Michael Bedford ^a   Miller, Jason ^a   Wentzlaff, David ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Power; Raw Microprocessor; Scalar Operand Network; Tile

Indexed keywords

ALGORITHMS; BANDWIDTH; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; DESIGN; ENERGY UTILIZATION; HEAT LOSSES; PROGRAM PROCESSORS; ROUTERS; VLSI CIRCUITS;

POWER; RAW MICROPROCESSORS; SCALAR OPERAND NETWORK; TITLE;

MICROPROCESSOR CHIPS;

EID: 85087534725     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/871604.871610     Document Type: Conference Paper

References (6)

1. Michael Taylor et al. The Raw Microprocessor. IEEE Micro, Apr 2002.
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3. Michael Taylor et al. Scalar Operand Networks: On-chip Interconnect for ILP in Partitioned Architectures. Proc. HPCA, Feb 2003.
4. H. Wang, et al. Power Model for Routers. IEEE Micro, Jan 2003.
5. Gunther, et al. Managing the Impact of Increasing Microprocessor Power Consumption. Intel Technology Journal. 1Q2001.
6. Walter Lee, et al. Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine. Proc. ASPLOS, 1998.