Accurate gate impedance determination on ultraleaky MOSFETs by fitting to a three-lumped-parameter model at frequencies from DC to RF

IEEE Transactions on Electron Devices

Volumn 54, Issue 7, 2007, Pages 1705-1712

  San Andrés, Enrique ^a   Pantisano, Luigi ^b   Ramos, Javier ^b   Roussel, Philippe J ^b   O'Sullivan, Barry J ^b   Toledano Luque, María ^a   DeGendt, Stefan ^b,c   Groeseneken, Guido ^b,c  

^a UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^b IMEC   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Capacitance measurement; MOSFET; Radio frequency (RF); Ultrathin gate dielectric

Indexed keywords

CONVENTIONAL THREE-LUMPED PARAMETER MODEL; RADIO FREQUENCY; THREE-LUMPED-PARAMETER MODEL; ULTRATHIN GATE DIELECTRIC;

ALGORITHMS; CAPACITANCE MEASUREMENT; GATE DIELECTRICS; GATES (TRANSISTOR); PARAMETER EXTRACTION; SEMICONDUCTOR DEVICE MODELS;

MOSFET DEVICES;

EID: 34447519132     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.898473     Document Type: Article

References (25)

1. C.-H. Choi, J.-S. Goo, T.-Y. Oh, Z. Yu, R. W. Dutton, A. Bayoumi, M. Cao, P. V. Voorde, D. Vook, and C. H. Diaz, "MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)," IEEE Electron Device Lett., vol. 20, no. 6, pp. 292-294, Jun. 1999.
2. G. A. Brown, "Capacitance characterization in integrated circuit development: The intimate relationship of test structure design, equivalent circuit, and measurement methodology," in Proc. IEEE ICMTS, 2005, pp. 213-217.
3. Y. Okawa, H. Norimatsu, H. Suto, and M. Takayanagi, "The negative capacitance effects on the C-V measurement of ultra thin gate dielectrics induced by the stray capacitance of the measurement system," in Proc. IEEE ICMTS, 2003, pp. 197-202.
4. P. A. Kraus, K. Z. Ahmed, and J. S. Williamson, "Elimination of chuckrelated parasitics in MOSFET gate capacitance measurements," IEEE Trans. Electron Devices, vol. 51, no. 8, pp. 1350-1352, Aug. 2004.
5. Z. Luo and T. P. Ma, "A new method to extract EOT of ultrathin gate dielectric with high leakage current," IEEE Electron Device Lett. vol. 25, no. 9, pp. 655-657, Sep. 2004.
6. J. Schmitz, F. N. Cubaynes, R. J. Havens, R. de Kort, A. J. Scholten, and L. F. Tiemeijer, "RF capacitance-voltage characterization of MOSFETs with high leakage dielectrics," IEEE Electron Device Lett. vol. 24, no. 1, pp. 37-39, Jan. 2003.
7. K. S. K. Kwa, S. Chattopadhyay, N. D. Jankovic, S. H. Olsern, L. S. Driscoll, and A. G. O'Neill, "A model for capacitance reconstruction from measured lossy MOS capacitance-voltage characteristics," Semicond. Sci. Technol., vol. 18, no. 2, pp. 82-87, Feb. 2003.
8. C. Yu, J. Zhang, J. S. Yuan, F. Duan, S. K. Jayanarananan, A. Marathe, S. Cooper, V. Pham, and J.-S. Goo, "Evaluation of RF capacitance extraction for ultrathin ultraleaky SOI MOS devices," IEEE Electron Device Lett., vol. 28, no. 1, pp. 45-47, Jan. 2007.
9. Y. L. Hsu, Y. K. Fang, F. C. Tsao, F. J. Kuo, and Y. Ho, "Modelling of abnormal capacitance-voltage characteristics observed in MOS transistors with ultra-thin gate oxide," Solid State Electron., vol. 46, no. 11, pp. 1941-1943, Nov. 2002.
10. S. H.-M. Jen, C. C. Enz, D. R. Pehlke, M. Schroter, and B. J. Sheu, "Accurate modelling and parameter extraction for MOS transistors valid up to 10 GHz," IEEE Trans. Electron Devices, vol. 46, no. 11, pp. 2217-2227, Nov. 1999.
11. A. Nara, N. Yausda, H. Satake, and A. Toriumi, "Applicability limits of the two frequency capacitance measurement technique for the thickness extraction of ultrathin gate oxide," IEEE Trans. Semicond. Manuf. vol. 15, no. 2, pp. 209-213, May 2002.
12. J. S. Goo, T. M. Mantei, K. Wieczorek, W. G. Enz, and A. B. Icel, "Extending two-element capacitance extraction method toward ultraleaky gate oxides using a short-channel length," IEEE Electron Device Lett., vol. 25, no. 12, pp. 819-821, Dec. 2004.
13. K. Ahmed, E. Ibok, G. C.-F. Yeap, Q. Xiang, B. Ogle, J. J. Wortman, and J. R. Hauser, "Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicongate depletion of sub-20-gate oxide MOSFET's," IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1650-1655, Aug. 1999.
14. D. W. Barlage, J. T. O'Keeffe, J. T. Kavalieros, M. M. Nguyen, and R. S. Chau, "Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit," IEEE Electron Device Lett., vol. 21, no. 9, pp. 454-456, Sep. 2000.
15. L. Pantisano, J. Ramos, E. San Andres, P. J. Roussel, W. Sansen, and G. Groeseneken, "A comprehensive model to accurately calculate gate capacitance and the leakage from dc to 100 MHz," in Proc. IEEE ICMTS 2006, pp. 222-225.
16. J. Schmitz, F. N. Cubaynes, R. J. Havens, R. de Kort, A. J. Scholten, and L. F. Tiemeijer, "Test structure design considerations for RF-CV measurements on leaky devices," IEEE Trans. Semicond. Manuf., vol. 17, no. 2, pp. 150-154, Feb. 2004.
17. K. J. Yang and C. Hu, "MOS capacitance measurements for high leakage thin dielectrics," IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1500-1501, Jul. 1999.
18. W. Jeamsaksiri, A. Mercha, J. Ramos, S. Decoutere, and F. Cubaynes, "RFCV test structure design for a selected frequency range," IEICE Trans. Electron., vol. E88-C, no. 5, pp. 817-823, May 2005.
19. M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J. G. Versleijen, "An improved de-embedding technique for on-wafer high-frequency characterization," in Proc. Bipolar Circuits and Technol. Meeting 1991, pp. 188-191.
20. A. Veloso, T. Hoffmann, A. Lauwers, S. Brus, J.-F. de Marneffe, S. Locorotondo et al., "Dual work function phase controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, reliability & process window improvement by sacrificial SiGe cap," in VLSI Symp. Tech. Dig., Honolulu, HI, 2006, pp. 94-95.
21. S. N. Hall, G. W. Hall, and J. A. McCall, High Speed Digital Design New York: Wiley, 2000.
22. J. Lin, C.-H. Chang, S. Prasad, and W. Loh, "An impedance-phase angle (Z-theta) method for capacitance extraction of ultra-thin gate dielectrics at intermediate frequency," in Proc. IEEE ICMTS, 2005, pp. 289-292.
23. W. Sansen and R. Meyer, "Characterization and measurement of the base and emitter resistances of bipolar transistors," IEEE J. Solid-State Circuits, vol. SSC-7, no. 6, pp. 492-498, Dec. 1972.
24. S. Severi, G. Curatola, C. Kerner, and K. De Meyer, "Accurate channel length extraction by split C-V measurements on short channel MOSFETs," IEEE Electron Device Lett., vol. 27, no. 7, pp. 615-618, Jul. 2006.
25. J. R. Hauser and K. Ahmed, "Characterization of ultra-thin oxides using electrical C-V and I-V measurements," in Characterization and Metrology for ULSI Technology, D. G. Seiler et al., Ed. Woodbury, NY: AIP, 1998, pp. 235-239.