MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)

IEEE Electron Device Letters

Volumn 20, Issue 6, 1999, Pages 292-294

  Choi, Chang Hoon ^a   Goo, Jung Suk ^a   Oh, Tae Young ^a   Yu, Zhiping ^a   Dutton, Robert W ^a   Bayoumi, Amr ^b   Cao, Min ^b   Voorde, Paul Vande ^b   Vook, Dieter ^b   Diaz, C H ^c  

^a Stanford University   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

^c NONE

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC ADMITTANCE; ELECTRON TUNNELING; EQUIVALENT CIRCUITS; GATES (TRANSISTOR); GREEN'S FUNCTION; MATHEMATICAL MODELS; OXIDES; QUANTUM THEORY;

SOFTWARE PACKAGE SPICE; ULTRATHIN GATE OXIDES;

MOS DEVICES;

EID: 0032689170     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.767102     Document Type: Article

References (6)

1. Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S. H. Lo, et al., "CMOS scaling into nanometer regime," Proc. IEEE. vol. 85, no. 4, p. 486, 1997.
2. Z. Yu, Stanford Univ., Stanford, CA, private communication.
3. M. J. van Dort, P. H. Woerlee, and A. J. Walker, "A simple model for quantization effects in heavily-doped silicon MOSFET's at inversion conditions," Solid-State Electron, vol. 37. no. 3. p. 411, 1994.
4. P. Vande Voorde, P. B. Griffin, Z. Yu, S-Y Oh, and R. W. Dutton, "Accurate doping profile determination using TED/QM models extensible to sub-quarter-micron nMOSFET's," in IEDM Tech. Dig., 1996, p. 811.
5. C. Bowen, et al., "Physical oxide thickness extraction and verification using quantum mechanical simulation," in IEDM Tech. Dig., 1997, p. 869.
6. 2 layer," J. Appl. Phys., vol. 75, no. 7, p. 3530, 1994.