A comprehensive model to accurately calculate the gate capacitance and the leakage from DC to 100 MHz for ultra thin dielectrics

IEEE International Conference on Microelectronic Test Structures

Volumn 2006, Issue , 2006, Pages 222-225

  Pantisano, L ^a   Ramos, J ^a   Serrano, E San Andrés ^a,b   Roussel, Ph J ^a   Sansen, W ^c   Groeseneken, G ^a,c  

^a IMEC   (Belgium)

^b UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

GATE CAPACITANCE; GATE LEAKAGE; PARASITIC EFFECTS; ULTRA THIN DIELECTRICS;

ALGORITHMS; CAPACITANCE; COMPUTER SIMULATION; ELECTRIC LINES; GATES (TRANSISTOR); LEAKAGE CURRENTS; ULTRATHIN FILMS;

DIELECTRIC MATERIALS;

EID: 33748491595     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMTS.2006.1614308     Document Type: Conference Paper

References (7)

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