The negative capacitance effect on the C-V measurement of ultra thin gate dielectrics induced by the stray capacitance of the measurement system

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2003, Pages 197-202

  Okawa, Yasushi ^a   Norimatsu, Hideyuki ^a   Suto, Hiroyuki ^b   Takayanagi, Mariko ^b  

^a YOKOGAWA ANALYTICAL SYSTEMS INC   (Japan)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC IMPEDANCE; GATES (TRANSISTOR); MOSFET DEVICES; ULTRATHIN FILMS;

NEGATIVE CAPACITANCE EFFECTS;

CAPACITANCE MEASUREMENT;

EID: 0037966281     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. M. Matsumura, Y. Hirose, "Negative-Capacitance Effect in Forward-Biased Metal Oxide Semiconductor Tunnel Diodes (MOSTD)", Jpn. J. Appl. Phys. Vol.39, pp. L123-L125, 2000.
2. M. Matsumura, Y. Hirose, "Extraction of a Metal Oxide Semiconductor Tunnel Diode (MOSTD) Based in Accumulation", Jpn. J. Appl. Phys. Vol.38, pp. L845-L847, 1999.
3. KJ. Yang, C. Hu, "MOS Capacitance Measurements for High-Leakage Thin Dielectrics", IEEE Trans. Elec. Dev. Vol.46, No.7, pp. 1500-1501, 1999.
4. W. K. Henson, K. Z. Ahmed, E. M. Vogel, J. R. Hauser, J. J. Wortman, R. D. Venables, M. Xu, D. Venables, "Estimating Oxide Thickness of Tunnel Oxides Down to 1.4nm Using Conventional Capacitance-Voltage Measurements on MOS Capacitors", IEEE Elec. Dev. Lett. Vol.20, No.4, pp. 179-181, 1999.
5. Agilent Technologies Impedance Measurement Handbook 2nd Edition.
6. H. Suto, Y. Okawa, M. Takayanagi, H. Norimatsu, Y. Toyoshima, "Methodology for Accurate C-V Measurement of Gate Insulators below 1.5nm EOT", Extended Abstract of the 2002 SSDM, pp. 748-749.