-
1
-
-
0033697180
-
Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors
-
T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," in VLSI Symp. Tech. Dig., 2000, pp. 174-175.
-
VLSI Symp. Tech. Dig., 2000
, pp. 174-175
-
-
Ghani, T.1
Mistry, K.2
Packan, P.3
Thompson, S.4
Stettler, M.5
Tyagi, S.6
Bohr, M.7
-
2
-
-
0033079368
-
On the tunneling component of charge pumping current in ultrathin gate oxide MOSFET's
-
Feb.
-
P. Masson, J.-L. Autran, and J. Brini, "On the tunneling component of charge pumping current in ultrathin gate oxide MOSFET's," IEEE Electron Device Lett., vol. 20, pp. 92-94, Feb. 1999.
-
(1999)
IEEE Electron Device Lett.
, vol.20
, pp. 92-94
-
-
Masson, P.1
Autran, J.-L.2
Brini, J.3
-
3
-
-
0012854580
-
Comparison of soft-breakdown triggers for large area capacitors
-
Sept.
-
J. Schmitz, H. P. Tuinhout, H. J. Kretschmann, and P. H. Woerlee, "Comparison of soft-breakdown triggers for large area capacitors," IEEE Trans. Device Mat. Rel., vol. 1, pp. 150-157, Sept. 2001.
-
(2001)
IEEE Trans. Device Mat. Rel.
, vol.1
, pp. 150-157
-
-
Schmitz, J.1
Tuinhout, H.P.2
Kretschmann, H.J.3
Woerlee, P.H.4
-
4
-
-
0032680955
-
Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors
-
Apr.
-
W. K. Henson, K. Z. Ahmed, E. M. Vogel, J. R. Hauser, J. J. Wortman, R. D. Venables, M. Xu, and D. Venables, "Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors," IEEE Electron Device Lett., vol. 20, pp. 179-181, Apr. 1999.
-
(1999)
IEEE Electron Device Lett.
, vol.20
, pp. 179-181
-
-
Henson, W.K.1
Ahmed, K.Z.2
Vogel, E.M.3
Hauser, J.R.4
Wortman, J.J.5
Venables, R.D.6
Xu, M.7
Venables, D.8
-
5
-
-
0012796004
-
Capacitance-voltage measurements and gate leakage
-
J. Schmitz, "Capacitance-voltage measurements and gate leakage," in Tutorial presented at the 2002 ICMTS Conference, Cork, Ireland.
-
2002 ICMTS Conference, Cork, Ireland
-
-
Schmitz, J.1
-
6
-
-
0032689170
-
MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)
-
June
-
C.-H. Choi, J.-S. Goo, T.-Y. Oh, Z. Yu, R. W. Dutton, A. Bayoumi, M. Cao, P. Vande Voorde, D. Vook, and C. H. Diaz, "MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)," IEEE Electron Device Lett., vol. 20, pp. 292-294, June 1999.
-
(1999)
IEEE Electron Device Lett.
, vol.20
, pp. 292-294
-
-
Choi, C.-H.1
Goo, J.-S.2
Oh, T.-Y.3
Yu, Z.4
Dutton, R.W.5
Bayoumi, A.6
Cao, M.7
Vande Voorde, P.8
Vook, D.9
Diaz, C.H.10
-
7
-
-
0032679052
-
MOS capacitance measurements for high-leakage thin dielectrics
-
July
-
K. J. Yang and C. Hu, "MOS capacitance measurements for high-leakage thin dielectrics," IEEE Trans. Electron Devices, vol. 46, pp. 1500-1501, July 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, pp. 1500-1501
-
-
Yang, K.J.1
Hu, C.2
-
8
-
-
0034258708
-
Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit
-
Sept.
-
D. W. Barlage, J. T. O'Keeffe, J. T. Kavalieros, M. M. Nguyen, and R. S. Chau, "Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit," IEEE Electron Device Lett., vol. 21, pp. 454-456, Sept. 2000.
-
(2000)
IEEE Electron Device Lett.
, vol.21
, pp. 454-456
-
-
Barlage, D.W.1
O'Keeffe, J.T.2
Kavalieros, J.T.3
Nguyen, M.M.4
Chau, R.S.5
-
9
-
-
0035715830
-
max realized at 0.18 μm gate length in an industrial RF-CMOS technology
-
max realized at 0.18 μm gate length in an industrial RF-CMOS technology," in IEDM Tech. Dig., 2001, pp. 223-226.
-
(2001)
IEDM Tech. Dig.
, pp. 223-226
-
-
Tiemeijer, L.F.1
Boots, H.M.J.2
Havens, R.J.3
Scholten, A.J.4
De Vreede, P.W.H.5
Woerlee, P.H.6
Heringa, A.7
Klaassen, D.B.M.8
-
10
-
-
0026679924
-
An improved de-embedding technique for on-wafer high frequency characterization
-
M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J. G. Versleijen, "An improved de-embedding technique for on-wafer high frequency characterization," in Proc. BCTM, 1991, pp. 188-191.
-
Proc. BCTM, 1991
, pp. 188-191
-
-
Koolen, M.C.A.M.1
Geelen, J.A.M.2
Versleijen, M.P.J.G.3
-
11
-
-
0012857007
-
-
[Online]. Available: http://www.semiconductors.philips.com/Philips_models.
-
-
-
-
12
-
-
2642523256
-
High-frequency response of 100nm integrated CMOS transistors with high-K gate dielectrics
-
D. W. Barlage, R. Arghavani, G. Dewey, M. Doczy, B. Doyle, J. T. Kavalieros, A. Murthy, B. Roberds, P. Stokley, and R. S. Chau, "High-frequency response of 100nm integrated CMOS transistors with high-K gate dielectrics," in IEDM Tech. Dig., 2001, pp. 231-234.
-
(2001)
IEDM Tech. Dig.
, pp. 231-234
-
-
Barlage, D.W.1
Arghavani, R.2
Dewey, G.3
Doczy, M.4
Doyle, B.5
Kavalieros, J.T.6
Murthy, A.7
Roberds, B.8
Stokley, P.9
Chau, R.S.10
|