Modeling of abnormal capacitance-voltage characteristics observed in MOS transistor with ultra-thin gate oxide

Solid-State Electronics

Volumn 46, Issue 11, 2002, Pages 1941-1943

  Hsu, Yung Lung ^a   Fang, Yean Kuen ^a   Tsao, Feng Cherng ^a   Kuo, Fu Jung ^a   Ho, Yens ^b  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Direct tunneling; HF LF curves; MOSFET; Ultra thin gate oxide

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; GATES (TRANSISTOR); MOSFET DEVICES;

CAPACITANCE-VOLTAGE (C-V) CURVES; ULTRA-THIN GATE OXIDES;

MOS DEVICES;

EID: 0036838762     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(02)00124-7     Document Type: Conference Paper

References (3)

1. Choi C.H., Goo J.S., Oh T.Y., Yu Z., Dutton R.W., Bayoumi A.et al. MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm). IEEE Electron. Dev. Lett. 20(6):1999;292-294.
2. Yuan T., Buchanan D.A., Chen W., Frank D.J., Ismail K.E., Lo S.-.H.et al. CMOS scaling into nanometer regime. Proc. IEEE. 85(4):1997;486-504.
3. Gordon B.J. C-V plotting myths and methods. Solid State Technol. (January):1993;57-61.