MOUSETRAP: High-speed transition-signaling asynchronous pipelines

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 6, 2007, Pages 684-698

  Singh, Montek ^a   Nowick, Steven M ^b  

^a University of North Carolina   (United States)

^b Department of Earth and Environmental Sciences   (United States)

Author keywords

Asynchronous; Clocked CMOS; Gate level pipelines; Latch controllers; Micropipelines; Pipeline processing; Transition signaling; Wave pipelining

Indexed keywords

ASYNCHRONOUS MACHINERY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CONTROL EQUIPMENT; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; SPICE;

CLOCKED CMOS; GATE LEVEL PIPELINES; LATCH CONTROLLERS; MICROPIPELINES; TRANSITION SIGNALING; WAVE PIPELINING;

PIPELINE PROCESSING SYSTEMS;

EID: 34250191827     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.898732     Document Type: Article

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