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Volumn , Issue , 1999, Pages 219-228

Two-phase asynchronous wave-pipelines and their application to a 2D-DCT

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS WAVES; BASIC STRUCTURE; CMOS PROCESSS; DISTRIBUTED ARITHMETIC; PIPELINE DESIGN; REQUEST SIGNALS; SYNCHRONOUS PARADIGM; THROUGHPUT RATE; VLSI SYSTEM;

EID: 77957943170     PISSN: 15228681     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1999.761536     Document Type: Conference Paper
Times cited : (9)

References (15)
  • 3
    • 0014617505 scopus 로고
    • Maximum-rate pipeline systems
    • Mont-vale, NJ: AFIPS Press May
    • L. W. Cotten, "Maximum-rate pipeline systems," AFIPS Proceedings Spring Joint Computer Conference, vol. 34, Mont-vale, NJ: AFIPS Press, pp. 581-586, May 1969.
    • (1969) AFIPS Proceedings Spring Joint Computer Conference , vol.34 , pp. 581-586
    • Cotten, L.W.1
  • 4
    • 0032204698 scopus 로고    scopus 로고
    • 64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency
    • Nov.
    • R. Heald et al., "64-KByte Sum-Addressed-Memory Cache with 1.6-ns Cycle and 2.6-ns Latency," IEEE Journal of Solid-Stale Circuits, vol. 33, no. 11, pp. 1682-1689, Nov. 1998.
    • (1998) IEEE Journal of Solid-Stale Circuits , vol.33 , Issue.11 , pp. 1682-1689
    • Heald, R.1
  • 5
  • 9
    • 0033361427 scopus 로고    scopus 로고
    • Efficient and safe asynchronous wave-pipeline architectures for datapath and control unit applications
    • March
    • O. Hauck, M. Garg, and S. A. Huss, "Efficient and Safe Asynchronous Wave-Pipeline Architectures for Datapath and Control Unit Applications," Proceedings Ninth Great Lakes Symposium on VLSI, March 1999.
    • (1999) Proceedings Ninth Great Lakes Symposium on VLSI
    • Hauck, O.1    Garg, M.2    Huss, S.A.3
  • 10
    • 0029233253 scopus 로고
    • Performance evaluation of asynchronous logic pipelines with data dependant processing delays
    • May
    • D. Kearney and N. Bergmann, "Performance Evaluation of Asynchronous Logic Pipelines with Data Dependant Processing Delays," Second Working Conf. on Asynchronous Design Methodologies, pp. 4-13, May 1995.
    • (1995) Second Working Conf. on Asynchronous Design Methodologies , pp. 4-13
    • Kearney, D.1    Bergmann, N.2
  • 13
    • 0024646951 scopus 로고
    • VLSI implementation of a 16 × 16 discrete cosine transform
    • April
    • M.-T. Sun, T.-C. Chen, and A. M. Gottlieb, "VLSI Implementation of a 16 × 16 Discrete Cosine Transform," IEEE Transactions on Circuits and Systems, vol. 36, no. 4, pp. 610-617, April 1989.
    • (1989) IEEE Transactions on Circuits and Systems , vol.36 , Issue.4 , pp. 610-617
    • Sun, M.-T.1    Chen, T.-C.2    Gottlieb, A.M.3
  • 15
    • 0032288788 scopus 로고    scopus 로고
    • Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor
    • Dec.
    • D. Johnson, V. Akella, and B. Stott, "Micropipelined Asynchronous Discrete Cosine Transform (DCT/IDCT) Processor," IEEE Transactions on VLSI, vol. 6, no. 4, pp. 731-740, Dec. 1998.
    • (1998) IEEE Transactions on VLSI , vol.6 , Issue.4 , pp. 731-740
    • Johnson, D.1    Akella, V.2    Stott, B.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.