High-performance asynchronous pipeline circuits

Proceedings - 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1996

Volumn , Issue , 1996, Pages 17-28

  Yun, K Y ^a   Beerel, P A ^b   Arceo, J ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Viterbi School of Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; DIGITAL STORAGE; INTEGRATED CIRCUIT DESIGN; PIPELINES; TIMING CIRCUITS;

ASYNCHRONOUS PIPELINE; CMOS PROCESSS; CONTROL STRUCTURE; CRITICAL PATHS; DESIGN AND SIMULATION; SPICE SIMULATIONS; STATE OF THE ART; TRANSMISSION GATE;

FLIP FLOP CIRCUITS;

EID: 67249133828     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1996.494434     Document Type: Conference Paper

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