MOUSETRAP: Ultra-high-speed transition-signaling asynchronous pipelines

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 9-17

  Singh, M ^a   Nowick, S M ^a  

^a Columbia University ^*  (United States)

Author keywords

Asynchronous pipelines; Clocked CMOS; Fine grain; Gate level pipelines; High throughput; Transition signaling; Transparent latches

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FLIP FLOP CIRCUITS; NETWORK PROTOCOLS;

ASYNCHRONOUS PIPELINES;

PIPELINE PROCESSING SYSTEMS;

EID: 0035186879     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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