-
2
-
-
0036474722
-
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
-
Feb.
-
K. A. Bowman, S. G. Duvall, and J. D. Meindl. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J. of Solid-State Circuits, 37(2): 183-190, Feb. 2002.
-
(2002)
IEEE J. of Solid-State Circuits
, vol.37
, Issue.2
, pp. 183-190
-
-
Bowman, K.A.1
Duvall, S.G.2
Meindl, J.D.3
-
4
-
-
0015605213
-
Anomalous behavior of synchronizer and arbiter circuits
-
Apr.
-
T. Chaney and C. Molnar. Anomalous behavior of synchronizer and arbiter circuits. IEEE Trans. on Computers, C-22(4):421-422, Apr. 1973.
-
(1973)
IEEE Trans. on Computers
, vol.C-22
, Issue.4
, pp. 421-422
-
-
Chaney, T.1
Molnar, C.2
-
5
-
-
0003657403
-
Globally-asynchronous, locally-synchronous systems
-
PhD thesis, Dept. of Computer Science, Stanford University, Oct.
-
D. M. Chapiro. Globally-Asynchronous, Locally-Synchronous Systems. PhD thesis, Dept. of Computer Science, Stanford University, Oct. 1984. Tech. Report STAN-CS-84-1026.
-
(1984)
Tech. Report STAN-CS-84-1026
-
-
Chapiro, D.M.1
-
6
-
-
0026257568
-
A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture
-
Nov.
-
T. I. Chappell, B. A. Chappell. et al. A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture. IEEE J. of Solid-State Circuits, 26(11):1577-1585, Nov. 1991.
-
(1991)
IEEE J. of Solid-State Circuits
, vol.26
, Issue.11
, pp. 1577-1585
-
-
Chappell, T.I.1
Chappell, B.A.2
-
7
-
-
0034853842
-
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
-
June
-
T. Chelcea and S. M. Nowick. Robust interfaces for mixed-timing systems with application to latency-insensitive protocols. In Proc. of the 38th ACM/IEEE Design Automation Conf., pages 21-26, June 2001.
-
(2001)
Proc. of the 38th ACM/IEEE Design Automation Conf.
, pp. 21-26
-
-
Chelcea, T.1
Nowick, S.M.2
-
8
-
-
0033281015
-
CMOS technology: Present and future
-
IEEE, June
-
B. Davari. CMOS technology: Present and future. In Proc. of 1999 Symp. on VLSI Circuits, pages 5-10. IEEE, June 1999.
-
(1999)
Proc. of 1999 Symp. on VLSI Circuits
, pp. 5-10
-
-
Davari, B.1
-
11
-
-
0036116742
-
A low-power RISC microprocessor using dual PLLs in a 0.1 3μ SOI technology with copper interconnect and low-k BEOL dielectric
-
Feb.
-
S. Geissler, D. Appenzeller, et al. A low-power RISC microprocessor using dual PLLs in a 0.1 3μ SOI technology with copper interconnect and low-k BEOL dielectric. In Proc. of the 2002 Int'l. Solid-State Circuits Conf., pages 148-149, Feb. 2002.
-
(2002)
Proc. of the 2002 Int'l. Solid-State Circuits Conf.
, pp. 148-149
-
-
Geissler, S.1
Appenzeller, D.2
-
14
-
-
0035707479
-
Statistical clock skew modeling with data delay variations
-
Dec.
-
D. Harris and S. Naffziger. Statistical clock skew modeling with data delay variations. IEEE Trans. on VLSI Systems, 9(1):888-898, Dec. 2001.
-
(2001)
IEEE Trans. on VLSI Systems
, vol.9
, Issue.1
, pp. 888-898
-
-
Harris, D.1
Naffziger, S.2
-
15
-
-
6644229433
-
A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit
-
DOI 10.1109/4.962281, PII S001892000108218X, 2001 ISSCC: Digital, Memory, and Signal Processing
-
G. Hinton, M. Upton, et al. A 0.18μ CMOS IA-32 processor with a 4-GHz integer execution unit. IEEE J. of Solid-Slate Circuits, 36(11):1617-1627, Nov. 2001. (Pubitemid 33105925)
-
(2001)
IEEE Journal of Solid-State Circuits
, vol.36
, Issue.11
, pp. 1617-1627
-
-
Hinton, G.1
Upton, M.2
Sager, D.J.3
Boggs, D.4
Carmean, D.M.5
Roussel, P.6
Chappell, T.I.7
Fletcher, T.D.8
Milshtein, M.S.9
Sprague, M.10
Samaan, S.11
Murray, R.12
-
16
-
-
0036294823
-
Power-performance evaluation of globally asynchronous, locally synchronous processors
-
June
-
A. Iyer and D. Marculescu. Power-performance evaluation of globally asynchronous, locally synchronous processors. In Proc. of the 29th Int'l. Symp. on Computer Architecture, pages 158-168, June 2002.
-
(2002)
Proc. of the 29th Int'l. Symp. on Computer Architecture
, pp. 158-168
-
-
Iyer, A.1
Marculescu, D.2
-
18
-
-
0036858658
-
Implementation of a third-generation 1.1-GHz 64-bit microprocessor
-
DOI 10.1109/JSSC.2002.803951
-
G. K. Konstadinidis, K. Normoyle, et al. Implementation of a third-generation 1.1-GHz 64-bit microprocessor. IEEE J. of Solid-State Circuits, 37(11):1461-1469, Nov. 2002. (Pubitemid 35432166)
-
(2002)
IEEE Journal of Solid-State Circuits
, vol.37
, Issue.11
, pp. 1461-1469
-
-
Konstadinidis, G.K.1
Normoyle, K.2
Wong, S.3
Bhutani, S.4
Stuimer, H.5
Johnson, T.6
Smith, A.7
Cheung, D.Y.8
Romano, F.9
Yu, S.10
Oh, S.-H.11
Melamed, V.12
Narayanan, S.13
Bunsey, D.14
Khieu, C.15
Wu, K.J.16
Schmitt, R.17
Dumlao, A.18
Sutera, M.19
Chau, J.20
Lin, K.J.21
Coates, W.S.22
more..
-
19
-
-
0002881388
-
ATLAS 1: Implmenting a single-chip ATM switch with backpressure
-
Jan/Feb
-
G. Kornaros, D. Pnevmatikatos, et al. ATLAS 1: Implmenting a single-chip ATM switch with backpressure. IEEE Micro, 19(1):30-41, Jan/Feb 1999.
-
(1999)
IEEE Micro
, vol.19
, Issue.1
, pp. 30-41
-
-
Kornaros, G.1
Pnevmatikatos, D.2
-
20
-
-
6644227176
-
The first MAJC microprocessor: A dual CPU system-on-a-chip
-
Nov.
-
A. Kowalczyk, V. Adler, et al. The first MAJC microprocessor: A dual CPU system-on-a-chip. IEEE J. of Solid-State Circuits, 36(11):1609-1916, Nov. 2001.
-
(2001)
IEEE J. of Solid-State Circuits
, vol.36
, Issue.11
, pp. 1609-1916
-
-
Kowalczyk, A.1
Adler, V.2
-
25
-
-
77957961901
-
Practical design of globally-asynchronous, locally-synchronous syterns
-
Apr.
-
J. Mutterbach, T. Villiger, and W. Fichtner. Practical design of globally-asynchronous, locally-synchronous syterns. In Proc. of the 6th Int'l. Symp. on Advanced Research in Asynchronous Circuits and Systems, pages 52-59, Apr. 2000.
-
(2000)
Proc. of the 6th Int'l. Symp. on Advanced Research in Asynchronous Circuits and Systems
, pp. 52-59
-
-
Mutterbach, J.1
Villiger, T.2
Fichtner, W.3
-
27
-
-
0035334849
-
A clock distribution network for microprocessors
-
May
-
P. J. Restle, T. G. McNamara, et al. A clock distribution network for microprocessors. IEEE J. of Solid-State Circuits, 36(5):792-799, May 2001.
-
(2001)
IEEE J. of Solid-State Circuits
, vol.36
, Issue.5
, pp. 792-799
-
-
Restle, P.J.1
McNamara, T.G.2
-
31
-
-
0034289978
-
Interfacing synchronous and asynchronous modules within a high-speed pipeline
-
Oct.
-
A. E. Sjogren and C. J. Myers. Interfacing synchronous and asynchronous modules within a high-speed pipeline. IEEE Trans. on VLSI Systems, 8(5):573-583, Oct. 2000.
-
(2000)
IEEE Trans. on VLSI Systems
, vol.8
, Issue.5
, pp. 573-583
-
-
Sjogren, A.E.1
Myers, C.J.2
-
33
-
-
0034317347
-
Clock generation and distribution for the first IA-64 microprocessor
-
DOI 10.1109/4.881198
-
S. Tarn, S. Rusu, et al. Clock generation and distribution for the first IA-64 microprocessor. IEEE J. of Solid-State Circuits, 35(11): 1545-1552, Nov. 2000. (Pubitemid 32070546)
-
(2000)
IEEE Journal of Solid-State Circuits
, vol.35
, Issue.11
, pp. 1545-1552
-
-
Tam, S.1
Rusu, S.2
Desai, U.N.3
Kim, R.4
Zhang, J.5
Young, I.6
-
34
-
-
2942669989
-
An event spacing experiment
-
Manchester, UK, Apr.
-
A. J. Winstanley, A. Garivier, and M. R. Greenstreet. An event spacing experiment. In Proc. of the Eigth Int'l. Symp. on Advanced Research in Asynchronous Circuits and Systems, pages 42-51, Manchester, UK, Apr. 2002.
-
(2002)
Proc. of the Eigth Int'l. Symp. on Advanced Research in Asynchronous Circuits and Systems
, pp. 42-51
-
-
Winstanley, A.J.1
Garivier, A.2
Greenstreet, M.R.3
-
35
-
-
0034318536
-
2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation
-
DOI 10.1109/4.881207
-
E. Yeung and M. A. Horowitz. A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation. IEEE J. of Solid-State Circuits, 35(11): 1619-1628, Nov. 2000. (Pubitemid 32070554)
-
(2000)
IEEE Journal of Solid-State Circuits
, vol.35
, Issue.11
, pp. 1619-1628
-
-
Yeung, E.1
Horowitz, M.A.2
|