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Volumn , Issue , 2000, Pages 198-209

High-throughput asynchronous pipelines for fine-grain dynamic datapaths

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS PIPELINE; CONTROL STRUCTURE; DATA ITEMS; DATA-PATHS; GRAIN DYNAMICS; HIGH THROUGHPUT; HSPICE SIMULATIONS; LOW LATENCY; MICRON TECHNOLOGIES; SINGLE GATES; TARGET DYNAMICS; TEST VEHICLE; WILLIAMS;

EID: 77957934332     PISSN: 15228681     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2000.837017     Document Type: Conference Paper
Times cited : (76)

References (18)
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  • 3
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    • Optimal clocking and enhanceditesta bility for high-performance self-resetting domino pipelines in proc
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  • 4
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    • Dynamic logic in four-phase micropipelines
    • S. B. Furben and J. Liu. Dynamic logic in four-phase micropipelines. In Proc. ASYNC, 1996.
    • (1996) Proc. ASYNC
    • Furben, S.B.1    Liu, J.2
  • 6
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    • Skew-tolerant domino circuits
    • November
    • D. Harris and M. A. Horowitz. Skew-tolerant domino circuits. IEEE JSSC, 32(11):1702-1711. November 1997.
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    • Harris, D.1    Horowitz, M.A.2
  • 7
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    • A doubly-latched asynchronous pipeline
    • R. Kol and R. Ginosar. A doubly-latched asynchronous pipeline. In Proc. ICCD, 1996.
    • (1996) Proc. ICCD
    • Kol, R.1    Ginosar, R.2
  • 9
    • 77957952475 scopus 로고    scopus 로고
    • A low power zero-overhead self-timed division and square root unit combining a single-rail static circuit with a dual-rail dynamic circuiit
    • G. Matsubara and N. Ide. A low power zero-overhead self-timed division and square root unit combining a single-rail static circuit with a dual-rail dynamic circuiit In ASYNC97.
    • ASYNC97
    • Matsubara, G.1    Ide, N.2
  • 13
    • 0030191609 scopus 로고    scopus 로고
    • New asynchronous pipeline scheme: Application to the design of a self-timed ring divider
    • July
    • M. Renaudin, B. Hassan, and A. Guyot. New asynchronous pipeline scheme: Application to the design of a self-timed ring divider. IEEE JSSC, 31(7):1001-1013, July 1996.
    • (1996) IEEE JSSC , vol.31 , Issue.7 , pp. 1001-1013
    • Renaudin, M.1    Hassan, B.2    Guyot, A.3
  • 17
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    • Designing high-performance digital circuits using wave-pipelining
    • January
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.