An adaptively-pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 GigaHertz

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2002, Pages 84-95

  Singh, Montek ^a   Tierno, Jose A ^b   Rylyakov, Alexander ^b   Rylov, Sergey ^b   Nowick, Steven M ^c  

^a UNIVERSITY OF NORTH CAROLINA   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c Department of Earth and Environmental Sciences   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDPASS FILTERS; CLOCKS; DIGITAL STORAGE; IMPULSE RESPONSE; MAXIMUM LIKELIHOOD; THROUGHPUT;

ASYNCHRONOUS PIPELINE; DISK DRIVE; GIGAS; HIGH-THROUGHPUT; LOW LATENCY; MODERN DISKS; PARTIAL RESPONSE MAXIMUM LIKELIHOOD; PERFORMANCE; READ CHANNELS; SYNCHRONOUS/ASYNCHRONOUS;

FIR FILTERS;

EID: 77957931942     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. Al Davis and Steven M. Nowick. Asynchronous circuit design: Motivation, background, and methods. In Graham Birtwistle and Al Davis, editors, Asynchronous Digital Circuit Design, Workshops in Computing, pages 1-49. Springer-Verlag, 1995.
2. G. Forney. Maximum-likelihood sequence estimation of digital sequences in the presence of intersymbol interference. IEEE Transactions on Information Theory, 18:363-378, May 1972.
3. S. B. Furber and J. Liu. Dynamic logic in four-phase micropipelines. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
4. K. Hwang. Computer Arithmetic: Principles, Architecture, and Design. Wiley, 1979.
5. H. Kobayashi and D. Tang. Application of partial-response channel coding to magnetic recording systems. IBM Journal of Research and Development, 14:368-375, July 1970.
6. A. Mukherjee, R. Sudhakar, M. Marek-Sadowska, and S.I. Long. Wave steering in YADDs: a novel non-iterative synthesis and layout technique. In Proc. ACM/IEEE Design Automation Conference, 1999.
7. A. V. Oppenheim and R. W. Schafer. Discrete-Time Signal Processing. Prentice Hall, 1989.
8. D.J. Pearson, S.K. Reynolds, A.C. Megdanis, S. Gowda, K.R. Wrenner, M. Immediato, R.L. Galbraith, and H.J. Shin. Digital FIR filters for high speed PRML disk read channels. IEEE Journal of Solid-Stale Circuits, 30(12):1517-1523, December 1995.
9. S. Rylov, A. Rylyakov, J. Tierno, M. Immediato, M. Beakes, M. Kapur, P. Ampadu, and D. Pearson. A 2.3 GSample/s 10-tap digital FIR filter for magnetic recording read channels. In International Solid State Circuits Conference, pages 190-191, February 2001.
10. Stanley Schuster, William Reohr, Peter Cook, David Heidel, Michael Immediato, and Keith Jenkins. Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz. In International Solid Slate Circuits Conference, February 2000.
11. Charles L. Seitz. System timing. In Carver A. Mead and Lynn A. Conway, editors, Introduction to VLSI Systems, chapter 7. Addison-Wesley, 1980.
12. Montek Singh and Steven M. Nowick. Fine-grain pipelined asynchronous adders for high-speed DSP applications. In Proceedings of the IEEE Computer Society Workshop on VLSI, pages 111-118. IEEE Computer Society Press, April 2000.
13. Montek Singh and Steven M. Nowick. High-throughput asynchronous pipelines for fine-grain dynamic datapaths. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 198-209. IEEE Computer Society Press, April 2000.
14. Ivan Sutherland and Scott Fairbanks. GasP: A minimal FIFO control. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 46-53. IEEE Computer Society Press, March 2001.
15. Jose Tierno, Alexander Rylyakov, Sergey Rylov, Montek Singh, Paul Ampadu, Steven Nowick, Michael Immediato, and Sudhir Gowda. A 1.3 GSample/s 10-tap full-rate variable-latency self-timed fir filter with clocked interfaces. In International Solid State Circuits Conference, San Francisco, CA, February 2002.
16. S. H. Unger. Asynchronous Sequential Switching Circuits. Wiley-Interscience, John Wiley & Sons, Inc., New York, 1969.
17. T. W. Williams and K. P. Parker. Design for testability-a survey. Proceedings of the IEEE, 31 (1): 18-22, January 1983.
18. Ted E. Williams. Self-Timed Rings and their Application to Division. PhD thesis, Stanford University, June 1991.
19. D.C. Wong, G. De Micheli, and M. Flynn. Designing high-performance digital circuits using wave-pipelining. IEEE Transactions on Computer-Aided Design, 12(1):24-46, January 1993.