Skew-tolerant domino circuits

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 11, 1997, Pages 1702-1711

  Harris, David ^a,b,c,d,e   Horowitz, Mark A ^a,e  

^a STANFORD UNIVERSITY   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^c Stanford University   (United States)

^d INTEL CORPORATION   (United States)

^e IEEE   (United States)

Author keywords

Adders; Clock skew; Clocks; CMOS digital integrated circuits; Dynamic logic; VLSI circuit design

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; TIMING CIRCUITS; VLSI CIRCUITS;

CLOCK SKEW; DOMINO CIRCUITS; DYNAMIC LOGIC; LATCH DELAY;

COMPUTER CIRCUITS;

EID: 0031273943     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.641690     Document Type: Article

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