Clock-delayed domino for adder and combinational logic design

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1996, Pages 332-337

  Yee, Gin ^a   Sechen, Carl ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMBINATORIAL CIRCUITS; COMPUTER AIDED LOGIC DESIGN; COMPUTER SIMULATION; DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT;

CLOCK DELAYED DOMINO (CD) CIRCUITS; DYNAMIC LOGIC;

LOGIC GATES;

EID: 0030409621     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)